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The following is copied from User talk:Rilak/02, where it resided as the article was being readied for release: Rilak ( talk) 11:05, 27 August 2008 (UTC)
-- Henriok ( talk) 10:55, 7 August 2008 (UTC)
Done. Not sure what RIOS is though. Rilak ( talk) 11:48, 7 August 2008 (UTC)
in order...
What is the difference between the RIOS1, RIOS-1 and the RIOS.9? These terms are not mentioned in the literature listed in the "references" section. Also, I have found this [1], which suggests that for a time, POWER2 was called RIOS2, which would mean that upgraded versions of the POWER1, the POWER1+ and POWER++ may also have RIOSn names before the introduction of the POWERn scheme. I would like to know the original names for the POWER1+ and POWER1++ so that they can be mentioned in the article. Rilak ( talk) 07:13, 18 August 2008 (UTC)
This PDF says: "The last POWER1 machine, announced in September of 1993, was the rack-mounted Model 990. It ran at 71.5 MHz and had a 32 KB I-cache and a 256 KB D-cache." It's presumably the POWER1++, and has four times as much I- and D-cache as RIOS-1. However.. this sounds very much like the POWER2. Is is possible that POWER++ _is_ the RIOS2, i.e. POWER2? -- Henriok ( talk)
Figure 2 in The IBM RISC System/6000 processor: Hardware overview shows 11 chips. We can easily account for 10 of them and what's in question is why the I/O unit sems to be split into two chips. For one, the SIO bus seems to be a double bus, and if onw takes a look at the POWER2 chip complex they are similar and they show two I/O units represented by two chips (off MCM). On page 7 in POWER2 Next generation of the RlSC System/6000 family it says that "The POWER2 I/0 unit is the same as the one in the RS/6000 Models 580 and 980", which are POWER1 based.. Even if it's clearly "original research" in Wikipedia terms, I think we can assume that the I/O unit in POWER1, at least in the 580 and 980 models, consists of two chips.
So.. I should probably revise the diagrams showing two I/O units and a Clock-chip. -- Henriok ( talk) 16:03, 21 August 2008 (UTC)
Well, I remember that the lowest-end machine had two less chips than the rest of them; I presume it was the D-cache. Although I could have sworn it was 9 and 7 not 11 ... linas ( talk) 21:29, 26 August 2012 (UTC)
I'd like to see more about how the FPU differed from the competition. At the time, it seemed rather revolutionary; when running misc codes in the lab, it would be done so fast, that at first, I thought there was a bug in the code or a bug in the OS. (as compared to e.g. SGI of the era, or HP or Sun). linas ( talk) 21:33, 26 August 2012 (UTC)
This article is rated C-class on Wikipedia's
content assessment scale. It is of interest to the following WikiProjects: | ||||||||||||||
|
The following is copied from User talk:Rilak/02, where it resided as the article was being readied for release: Rilak ( talk) 11:05, 27 August 2008 (UTC)
-- Henriok ( talk) 10:55, 7 August 2008 (UTC)
Done. Not sure what RIOS is though. Rilak ( talk) 11:48, 7 August 2008 (UTC)
in order...
What is the difference between the RIOS1, RIOS-1 and the RIOS.9? These terms are not mentioned in the literature listed in the "references" section. Also, I have found this [1], which suggests that for a time, POWER2 was called RIOS2, which would mean that upgraded versions of the POWER1, the POWER1+ and POWER++ may also have RIOSn names before the introduction of the POWERn scheme. I would like to know the original names for the POWER1+ and POWER1++ so that they can be mentioned in the article. Rilak ( talk) 07:13, 18 August 2008 (UTC)
This PDF says: "The last POWER1 machine, announced in September of 1993, was the rack-mounted Model 990. It ran at 71.5 MHz and had a 32 KB I-cache and a 256 KB D-cache." It's presumably the POWER1++, and has four times as much I- and D-cache as RIOS-1. However.. this sounds very much like the POWER2. Is is possible that POWER++ _is_ the RIOS2, i.e. POWER2? -- Henriok ( talk)
Figure 2 in The IBM RISC System/6000 processor: Hardware overview shows 11 chips. We can easily account for 10 of them and what's in question is why the I/O unit sems to be split into two chips. For one, the SIO bus seems to be a double bus, and if onw takes a look at the POWER2 chip complex they are similar and they show two I/O units represented by two chips (off MCM). On page 7 in POWER2 Next generation of the RlSC System/6000 family it says that "The POWER2 I/0 unit is the same as the one in the RS/6000 Models 580 and 980", which are POWER1 based.. Even if it's clearly "original research" in Wikipedia terms, I think we can assume that the I/O unit in POWER1, at least in the 580 and 980 models, consists of two chips.
So.. I should probably revise the diagrams showing two I/O units and a Clock-chip. -- Henriok ( talk) 16:03, 21 August 2008 (UTC)
Well, I remember that the lowest-end machine had two less chips than the rest of them; I presume it was the D-cache. Although I could have sworn it was 9 and 7 not 11 ... linas ( talk) 21:29, 26 August 2012 (UTC)
I'd like to see more about how the FPU differed from the competition. At the time, it seemed rather revolutionary; when running misc codes in the lab, it would be done so fast, that at first, I thought there was a bug in the code or a bug in the OS. (as compared to e.g. SGI of the era, or HP or Sun). linas ( talk) 21:33, 26 August 2012 (UTC)