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A diagram could help clarify and remove ambiguity. I feel unclear about what components there are, and the relationship between them, or the physical connections between them. Rsamot ( talk) 03:21, 12 June 2012 (UTC)
The first channel is usually considered to be the IBM 709's model 766 data synchronizer, shipped in about 1957. The 7090, announced in 1958 and shipped in 1969 supported the 766 and also the more advanced 7607 channel and 7606 multiplexor. These both significantly predate the 6600 which didn't ship until 1964. See http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7090B.html John L 20:36, 16 September 2007 (UTC)
I encountered an odd question embedded in a comment within the article that would have been better put on the talk page. The comment read:
huh|date=April 2008 … it doesn't use main memory? why?
Independent processors and coprocessors can't use main memory as scratchpad because it would interfere with the operation of programs already in main memory. They have to have independent counters and memory for addressing that doesn't conflict with the main unit.
However, DMA controllers will read the desired data directly into main memory or write the indicated data directly from main memory.
Does that clarify?
regards, -- UnicornTapestry ( talk) 02:28, 7 January 2009 (UTC)
IMO Sections 4 thru 6 of this article has recently become too specific to IBM Channels as opposed to I/O Channels in general, e.g. recent edits by User:Peterh5322. Perhaps the simple thing to do is make these three current sections into subsections of one new Section "4. IBM Channel I/O as an example". Tom94022 ( talk) 18:25, 23 December 2014 (UTC)
Shmuel (Seymour J.) Metz Username:Chatul ( talk) 18:45, 9 December 2019 (UTC)
We might look to Smotherman's "A Survey and Taxonomy of I/O Systems" along with his cited references as a reliable starting point for revising this article. Smotherman also suggest a rewrite of Input/Output is in order. Tom94022 ( talk) 17:12, 26 May 2020 (UTC)
Notes
References
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I know there have been discussions of this elsewhere. Even IBM has been inconsistent; The original IBM System/360 System Summary (1964) uses "multiplexor". [1]
On the other hand this article is not IBM-specific. The google ngram viewer shows "multiplexer" with a significant lead—at one point 2 to one and now about 10 to 1. [2] Perhaps we should use "multiplexer" consistently and then list "multiplexor" as an alternate spelling. Comments? Peter Flass ( talk) 21:25, 19 January 2018 (UTC)
{{
cite web}}
: |last1=
has generic name (
help)
See #Too IBM Specific? and Talk:Execute_Channel_Program#Duplicate_info for discussion. Peter Flass ( talk) 16:19, 6 December 2019 (UTC)
The implied CCW description doesn't seem like I thought I knew at. As well as I know, there is an implied CCW at location 0 that does the 24 byte read into location 8. I believe that a possible implementation (maybe used in some machines) is for the IPL logic to write an actual CCW into location 0 and SIO it. That is, I believe that IBM documented it that way somewhere. Since the real or implied CCW will be overwritten, there is normally no way for the user to know. I suspect that if it fails, it might be visible in storage after the failure. Gah4 ( talk) 23:01, 12 May 2020 (UTC)
When the I/O operations and psw loading are not completed satisfactorily, the CPU idles, and the load light remains.
Channel I/O#History states One of the earliest non-IBM channel systems was hosted in the
CDC 6600
supercomputer in 1965.
However, both the
CDC 1604 and
UNIVAC 1107 were well before that.
Shmuel (Seymour J.) Metz Username:Chatul (
talk) 13:02, 31 March 2021 (UTC)
Channel I/O#History states However, with the rapid speed increases in computers today, combined with
operating systems that don't 'block' when waiting for data, channel controllers have become correspondingly less effective and are not commonly found on small machines.
That text has unsubstantiated conclusions:
Shmuel (Seymour J.) Metz Username:Chatul ( talk) 13:08, 31 March 2021 (UTC)
References
{{
cite book}}
: |work=
ignored (
help)
Talk:Channel I/O#Channel programs in virtual storage systems is oriented towards IBM OS/VS in general and MVS in particular. It does not describe systems such as DOS/VSE [1] with ECPS:VSE, where the channel controller handles translation of virtual addresses in the CCWs, nor does it describe channel I/O on capability based systems. Shmuel (Seymour J.) Metz Username:Chatul ( talk) 02:37, 2 May 2021 (UTC)
References
{{
cite book}}
: |work=
ignored (
help)
@
Maury Markowitz: In a recent edit to
Channel I/O#history,
Maury Markowitz changed the text Channel architecture avoids this problem by using a logically independent, low-cost facility.
to Channel architecture avoids this problem by using a logically independent, low-cost processor dedicated to the I/O task.
I reverted the change with the comment t wasn't always a processor
and he reinstated his change. On some computers the I/O channels were implemented with cycle stealing from the CPU and the only dedicated hardware was a few registers and an interface to the channel bus. Perhaps facility is too terse, but processor is misleading at best. Perhaps facility with a footnote?
He also added two {{ clarify}} templates. I added wikilinks to channel commands and command chaining; is that sufficient to remove the {{ clarify}} templates?
Is it appropriate to add citations for channel commands and chaining, and, if so, how many would be reasonable? -- Shmuel (Seymour J.) Metz Username:Chatul ( talk) 20:15, 24 December 2021 (UTC)
8.5 Channel - Concept
A channel is a peripheral processor so specialized for the transmission of I/O data that it cannot perform the normal main-processor operations, even at reduced power or efficiency. Since transmission is most of I/O activity, a channel does most of the I/O work, in terms of time fraction. ... In contrast to the PPU, however, the channel has no explicit memory space of its own, the channel program therefore resides in main memory.
Computer Architecture, Blauuw and Brooks, Chapter 8 Input/Output
References
{{
cite book}}
: |work=
ignored (
help)
I believe that #Types of channels should be organized as
I'm not sure what to do about Externally Specified Index (ESI) on, e.g., UNIVAC 490. I also don't know how many examples to give of each type.
Similarly, #Channel program should be split into separate section. -- Shmuel (Seymour J.) Metz Username:Chatul ( talk) 19:12, 3 February 2022 (UTC)
The article says: On the 303x processor complexes, IBM abandoned that implementation and used the same cycle-stealing implementation as on the 370/158. No subsequent product in the System/360 line had hardwired channels. As I understand it, they used an actual (returned from lease) 370/158 with new microcode for, at least, 3033 and I believe 3032. Maybe not the 3031. So it isn't cycle stealing, as it is a separate processor, after it has the new microcode. Gah4 ( talk) 23:16, 30 April 2022 (UTC)
On the 303x processor complexes, the channels were implemented in independent channel directors in the same cabinet as the CPU, with each channel director implementing a group of channels.with a reference from an IBM document. I wouldn't call that "cycle stealing" in the "is the CPU involved in data transfer?" sense, which I think is the most meaningful sense; maybe different channels have to share the 3158-3's hardware, but the CPUs don't - they have their own hardware to run S/370 instructions. Guy Harris ( talk) 07:40, 24 May 2023 (UTC)
This article was the subject of an educational assignment supported by Wikipedia Ambassadors through the India Education Program.
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This article is rated C-class on Wikipedia's
content assessment scale. It is of interest to the following WikiProjects: | ||||||||||||||||||||||||||||
|
Please place new discussions at the bottom of the talk page. |
This is the
talk page for discussing improvements to the
Channel I/O article. This is not a forum for general discussion of the article's subject. |
Article policies
|
Find sources: Google ( books · news · scholar · free images · WP refs) · FENS · JSTOR · TWL |
A diagram could help clarify and remove ambiguity. I feel unclear about what components there are, and the relationship between them, or the physical connections between them. Rsamot ( talk) 03:21, 12 June 2012 (UTC)
The first channel is usually considered to be the IBM 709's model 766 data synchronizer, shipped in about 1957. The 7090, announced in 1958 and shipped in 1969 supported the 766 and also the more advanced 7607 channel and 7606 multiplexor. These both significantly predate the 6600 which didn't ship until 1964. See http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7090B.html John L 20:36, 16 September 2007 (UTC)
I encountered an odd question embedded in a comment within the article that would have been better put on the talk page. The comment read:
huh|date=April 2008 … it doesn't use main memory? why?
Independent processors and coprocessors can't use main memory as scratchpad because it would interfere with the operation of programs already in main memory. They have to have independent counters and memory for addressing that doesn't conflict with the main unit.
However, DMA controllers will read the desired data directly into main memory or write the indicated data directly from main memory.
Does that clarify?
regards, -- UnicornTapestry ( talk) 02:28, 7 January 2009 (UTC)
IMO Sections 4 thru 6 of this article has recently become too specific to IBM Channels as opposed to I/O Channels in general, e.g. recent edits by User:Peterh5322. Perhaps the simple thing to do is make these three current sections into subsections of one new Section "4. IBM Channel I/O as an example". Tom94022 ( talk) 18:25, 23 December 2014 (UTC)
Shmuel (Seymour J.) Metz Username:Chatul ( talk) 18:45, 9 December 2019 (UTC)
We might look to Smotherman's "A Survey and Taxonomy of I/O Systems" along with his cited references as a reliable starting point for revising this article. Smotherman also suggest a rewrite of Input/Output is in order. Tom94022 ( talk) 17:12, 26 May 2020 (UTC)
Notes
References
Hello fellow Wikipedians,
I have just modified 2 external links on Channel I/O. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
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This message was posted before February 2018.
After February 2018, "External links modified" talk page sections are no longer generated or monitored by InternetArchiveBot. No special action is required regarding these talk page notices, other than
regular verification using the archive tool instructions below. Editors
have permission to delete these "External links modified" talk page sections if they want to de-clutter talk pages, but see the
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source check}}
(last update: 5 June 2024).
Cheers.— InternetArchiveBot ( Report bug) 09:43, 14 January 2018 (UTC)
I know there have been discussions of this elsewhere. Even IBM has been inconsistent; The original IBM System/360 System Summary (1964) uses "multiplexor". [1]
On the other hand this article is not IBM-specific. The google ngram viewer shows "multiplexer" with a significant lead—at one point 2 to one and now about 10 to 1. [2] Perhaps we should use "multiplexer" consistently and then list "multiplexor" as an alternate spelling. Comments? Peter Flass ( talk) 21:25, 19 January 2018 (UTC)
{{
cite web}}
: |last1=
has generic name (
help)
See #Too IBM Specific? and Talk:Execute_Channel_Program#Duplicate_info for discussion. Peter Flass ( talk) 16:19, 6 December 2019 (UTC)
The implied CCW description doesn't seem like I thought I knew at. As well as I know, there is an implied CCW at location 0 that does the 24 byte read into location 8. I believe that a possible implementation (maybe used in some machines) is for the IPL logic to write an actual CCW into location 0 and SIO it. That is, I believe that IBM documented it that way somewhere. Since the real or implied CCW will be overwritten, there is normally no way for the user to know. I suspect that if it fails, it might be visible in storage after the failure. Gah4 ( talk) 23:01, 12 May 2020 (UTC)
When the I/O operations and psw loading are not completed satisfactorily, the CPU idles, and the load light remains.
Channel I/O#History states One of the earliest non-IBM channel systems was hosted in the
CDC 6600
supercomputer in 1965.
However, both the
CDC 1604 and
UNIVAC 1107 were well before that.
Shmuel (Seymour J.) Metz Username:Chatul (
talk) 13:02, 31 March 2021 (UTC)
Channel I/O#History states However, with the rapid speed increases in computers today, combined with
operating systems that don't 'block' when waiting for data, channel controllers have become correspondingly less effective and are not commonly found on small machines.
That text has unsubstantiated conclusions:
Shmuel (Seymour J.) Metz Username:Chatul ( talk) 13:08, 31 March 2021 (UTC)
References
{{
cite book}}
: |work=
ignored (
help)
Talk:Channel I/O#Channel programs in virtual storage systems is oriented towards IBM OS/VS in general and MVS in particular. It does not describe systems such as DOS/VSE [1] with ECPS:VSE, where the channel controller handles translation of virtual addresses in the CCWs, nor does it describe channel I/O on capability based systems. Shmuel (Seymour J.) Metz Username:Chatul ( talk) 02:37, 2 May 2021 (UTC)
References
{{
cite book}}
: |work=
ignored (
help)
@
Maury Markowitz: In a recent edit to
Channel I/O#history,
Maury Markowitz changed the text Channel architecture avoids this problem by using a logically independent, low-cost facility.
to Channel architecture avoids this problem by using a logically independent, low-cost processor dedicated to the I/O task.
I reverted the change with the comment t wasn't always a processor
and he reinstated his change. On some computers the I/O channels were implemented with cycle stealing from the CPU and the only dedicated hardware was a few registers and an interface to the channel bus. Perhaps facility is too terse, but processor is misleading at best. Perhaps facility with a footnote?
He also added two {{ clarify}} templates. I added wikilinks to channel commands and command chaining; is that sufficient to remove the {{ clarify}} templates?
Is it appropriate to add citations for channel commands and chaining, and, if so, how many would be reasonable? -- Shmuel (Seymour J.) Metz Username:Chatul ( talk) 20:15, 24 December 2021 (UTC)
8.5 Channel - Concept
A channel is a peripheral processor so specialized for the transmission of I/O data that it cannot perform the normal main-processor operations, even at reduced power or efficiency. Since transmission is most of I/O activity, a channel does most of the I/O work, in terms of time fraction. ... In contrast to the PPU, however, the channel has no explicit memory space of its own, the channel program therefore resides in main memory.
Computer Architecture, Blauuw and Brooks, Chapter 8 Input/Output
References
{{
cite book}}
: |work=
ignored (
help)
I believe that #Types of channels should be organized as
I'm not sure what to do about Externally Specified Index (ESI) on, e.g., UNIVAC 490. I also don't know how many examples to give of each type.
Similarly, #Channel program should be split into separate section. -- Shmuel (Seymour J.) Metz Username:Chatul ( talk) 19:12, 3 February 2022 (UTC)
The article says: On the 303x processor complexes, IBM abandoned that implementation and used the same cycle-stealing implementation as on the 370/158. No subsequent product in the System/360 line had hardwired channels. As I understand it, they used an actual (returned from lease) 370/158 with new microcode for, at least, 3033 and I believe 3032. Maybe not the 3031. So it isn't cycle stealing, as it is a separate processor, after it has the new microcode. Gah4 ( talk) 23:16, 30 April 2022 (UTC)
On the 303x processor complexes, the channels were implemented in independent channel directors in the same cabinet as the CPU, with each channel director implementing a group of channels.with a reference from an IBM document. I wouldn't call that "cycle stealing" in the "is the CPU involved in data transfer?" sense, which I think is the most meaningful sense; maybe different channels have to share the 3158-3's hardware, but the CPUs don't - they have their own hardware to run S/370 instructions. Guy Harris ( talk) 07:40, 24 May 2023 (UTC)
This article was the subject of an educational assignment supported by Wikipedia Ambassadors through the India Education Program.
The above message was substituted from {{IEP assignment}}
by
PrimeBOT (
talk) on 20:07, 1 February 2023 (UTC)
Cite error: There are <ref group=lower-alpha>
tags or {{efn}}
templates on this page, but the references will not show without a {{reflist|group=lower-alpha}}
template or {{notelist}}
template (see the
help page).