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Submission declined on 6 January 2024 by
Lewcm (
talk). This submission is not adequately supported by
reliable sources. Reliable sources are required so that information can be
verified. If you need help with referencing, please see
Referencing for beginners and
Citing sources. |
CRUVI is an expansion bus interface designed to create an open ecosystem of function modules for high-performance peripheral connectivity. Its main focus is on supporting FPGA and FPGA SoC devices from all major manufacturers like Intel ®, Lattice, Microchip and Xilinx.
The word "CRUVI" is a combination of the Estonian word "KRUVI" for screw and the letter "C", which refers to the half of the hexagonal screw head. In this case, the "K" was replaced with "C" to emphasize the reference to the screw head.
The CRUVI open standard coexists between low speed, low pin-count like Pmod Interface devices and high-performance, high pin-count ( HPC), 400 I/O FPGA Mezzanine Card (FMC) peripherals.
It can be used to build high performance prototypes, for system integration and testing to build complex systems from smaller building blocks to iterate quickly and reduce cost. Create custom test systems for production functional testing. It's a perfect platform for your next high-performance semiconductor evaluation boards and systems.
Interface bridging to or from other coexistence ecosystem is possible to do with peripheral modules or boards.
Three board-to-board connectors are specified: CRUVI-LS (Low Speed), CRUVI-HS (High Speed) and CRUVI-GT ( Gigabit Transceiver) PCIe Gen 5.0 capable.
Peripheral CRUVI-HS and CRUVI-GT test board with loopback, scope or logic analyzer functions can verify the i.e. high speed connector performance or to be probed signals. [1]
International contributors to define the open source CRUVI specification are Trenz Electronic GmbH, Arrow Electronics, Samtec, Flinders University, Synaptic Laboratories Ltd, Symbiotic EDA and MicroFPGA UG.
History of CRUVI open source specification – FREE to use Apache License 2.0
Year | Version | Notes | Refs |
---|---|---|---|
2021 | 1.0.7 -alpha | first release | [1] |
2024 | 2.0.1 -alpha | coming soon |
Carrier board or host board delivers power supplies, IO voltage and controls the functions of peripheral modules.
Single, double or triple width modules are allowed and they have more mounting holes.
A triple size of space on carrier board (PCB template CR99201) is 2.666 inches by 2.264 inches (67.72 mm × 57.5 mm) with LS and HS connectors. There are 3 slots named: AX, BY, and CZ. The mounting holes (1 to 6) for M2 screws are 2.2 mm (0.0866 inch) diameter and need SMD spacer for mechanically fixing. [1]
It is recommended for all FPGA host boards with CRUVI slots provide LiteX platform support files. [2]
Host and carrier boards are available with FPGA´s from Intel ® (TEI0050, TEI0185 [3], CR00010, CR00100, CR00109), Lattice (TEL003, CR00103), Microchip (TEMB0005) and Xilinx (TEBF0707, CR00107). [4]
Bridging adapter exists to convert signals from Pmod to CRUVI-LS (CR00025), from FMC to CRUVI-HS (CR00101, CR00111) and FMC to CRUVI-GT (CR00112). [1]
There are different single peripheral module possible, flexible and scalable by size LS, HS and GT connectors. Mounting holes are for M2 screws 2.2 millimeters (0.087 in) diameter.
It is recommended to have EEPROM with I2C for identification of peripheral module with a specific address number.
L × H | speed | PCB template [5] | Note |
---|---|---|---|
14 mm × 14 mm (0.55 in × 0.55 in) |
LS | CR99001 |
identification EEPROM is included; This template is usefull for I2C, I3C, SPI sensor, I2S PDM MEMS microphones, programmable oscillator, ADC, DAC or SPI (QSPI) Flash memory device in BGA24 or SO-8 package. |
14 mm × 14 mm (0.55 in × 0.55 in) |
LS | CR99002 | same as CR99001 with added u.Fl connectors for I/O |
22 mm × 32 mm (0.87 in × 1.26 in) |
LS | CR99003 |
maximum size one-wide half-length, identification EEPROM is included |
18 mm × 32 mm (0.71 in × 1.26 in) |
LS | CR99004 |
This template is useful to convert into Pmod compatible connector. |
22 mm × 30 mm (0.87 in × 1.18 in) |
LS | CR99005 |
is half-length LS module with two SMA connectors |
18 mm × 20 mm (0.71 in × 0.79 in) |
HS | CR99101 |
minimal size HS Module; good for HyperRAM or HyperFlash, eMMC or loopback adapter for CRUVI-HS |
22 mm × 57.5 mm (0.87 in × 2.26 in) |
HS | CR99102 |
maximum sized single-width HS module; good for signal test adapter to probed with scope or logic analyzer, for high speed interfaces like USB-C, HDMI, MIPI CSI/ DSI, SDIO, xGMII Ethernet and LVDS ADC (1 to 4 data lane) |
Connector | LS Low Speed | HS High Speed | GT Gigabit Transceiver |
---|---|---|---|
Carrier side connector | CLT-106-02-F-D-A-K | SS4-30-3.50-L-D-K | ADF6-20-03.5-L-4-2 |
Peripheral side connector | TMMH-106-04-F-DV-A-M | ST4-30-1.50-L-D-P | ADM6-20-01.5-L-4-2 |
Pin no | 12 (6 per row) | 60 (30 per row) | 80 (20 per row) |
pitch | 2 mm (0.079 in) | 0.4 mm (0.016 in) | 0.635 mm (0.0250 in) |
stacked height | 4.78 mm (0.188 in) to 5.29 mm (0.208 in) | 5 mm (0.20 in) | |
speed rating [GHz] / [Gbps] | 5.5 / 11 | 13.5 / 27 (single ended)
15.5 / 31 (differential) |
32 |
Single ended I/O pins (VCCIO) | 8 | 37 (28 adj.) + (9 fixed 3.3V) | 8 + I2C |
max. differential I/O | no | max. 12 LVDS | max. 4 lanes + REFCLK |
Power Supply | adj., 3.3V, 5V | ||
Current rating per pin [A] | 4.1 (2-pin powered) | 1.6 (2-pin powered) | 1.34 (4-pin powered) |
max. Temperatur range [°C] | −55 to 125 |
Pin | Primary | Signal | Pin | Primary | Signal |
---|---|---|---|---|---|
1 | SDA | I2C(SDA), SMBUS(SDA) | 7 | D1 | UART(RXD1), SD(D1), SPI(MISO), QSPI(D1), JTAG(TDI) |
2 | SCL | I2C(SCL), SMBUS(SCL) | 8 | CLK | UART(RTS), SD(CLK), SPI(CLK), QSPI(CLK), JTAG(TCK) |
3 | D3 | UART(RST), SD(TXD0), QSPI(D3), JTAG(nRST) | 9 | D0 | UART(TXD1), SD(D0), SPI(MOSI), QSPI(D0) JTAG(TDO) |
4 | SEL | UART(CTS), SD(CMD), SPI(SEL), QSPI(SEL), JTAG(TMS) | 10 | VCC | Power 3.3V |
5 | D2 | SMBUS(INT), UART(RXD0), SD(D2), QSPI(D2), JTAG(RFU) | 11 | RFU | tbd |
6 | GND | Ground | 12 | VBUS | Power 5V |
Pin | Primary Function | Note | Pin | Primary Function | Note | Pin | Primary Function | Note | Pin | Primary Function | Note |
---|---|---|---|---|---|---|---|---|---|---|---|
1 | RFU1 | 16 | A0_N | Transceiver I/O | 31 | GND | Ground | 46 | A5_N | Transceiver I/O | |
2 | HSIO | 17 | B0_N | Transceiver I/O | 32 | A3_P | 47 | B5_N | Transceiver I/O | ||
3 | ALERT/IRQ | 18 | GND | Ground | 33 | B3_P | Transceiver I/O | 48 | GND | Ground | |
4 | VCC | 3,3V | 19 | GND | Ground | 34 | A3_N | 49 | GND | Ground | |
5 | SDA | 20 | A1_P | Transceiver I/O | 35 | B3_N | Transceiver I/O | 50 | RFU2_P | ||
6 | HSO | 21 | B1_P | Transceiver I/O | 36 | VADJ | 1.2 to 3.3V | 51 | DI/TDI | JTAG, SPI(MISO) | |
7 | SCL | 22 | A1_N | Transceiver I/O | 37 | GND | Ground | 52 | RFU2_N | ||
8 | HSRST | 23 | B1_N | Transceiver I/O | 38 | A4_P | Transceiver I/O | 53 | DO/TDO | JTAG, SPI(MOSI) | |
9 | VCC | 3.3V | 24 | GND | Ground | 39 | B4_P | Transceiver I/O | 54 | GND | Ground |
10 | HSI | 25 | GND | Ground | 40 | A4_N | Transceiver I/O | 55 | SEL/TMS | JTAG, SPI(SEL) | |
11 | REFCLK | 26 | A2_P | 41 | B4_N | Transceiver I/O | 56 | RFU_P | |||
12 | GND | Ground | 27 | B2_P | Transceiver I/O | 42 | GND | Ground | 57 | MODE | JTAG EN |
13 | GND | Ground | 28 | A2_N | 43 | GND | Ground | 58 | RFU_N | ||
14 | A0_P | Transceiver I/O | 29 | B2_N | Transceiver I/O | 44 | A5_P | Transceiver I/O | 59 | SCK/TCK | JTAG, SPI(CLK) |
15 | B0_P | Transceiver I/O | 30 | GND | Ground | 45 | B5_P | Transceiver I/O | 60 | VBUS | 5V |
Submission declined on 31 March 2024 by
ToadetteEdit (
talk). This submission is not adequately supported by
reliable sources. Reliable sources are required so that information can be
verified. If you need help with referencing, please see
Referencing for beginners and
Citing sources. This draft's references do not show that the subject
qualifies for a Wikipedia article. In summary, the draft needs multiple published sources that are:
Where to get help
How to improve a draft
You can also browse Wikipedia:Featured articles and Wikipedia:Good articles to find examples of Wikipedia's best writing on topics similar to your proposed article. Improving your odds of a speedy review To improve your odds of a faster review, tag your draft with relevant WikiProject tags using the button below. This will let reviewers know a new draft has been submitted in their area of interest. For instance, if you wrote about a female astronomer, you would want to add the Biography, Astronomy, and Women scientists tags. Editor resources
|
Submission declined on 6 January 2024 by
Lewcm (
talk). This submission is not adequately supported by
reliable sources. Reliable sources are required so that information can be
verified. If you need help with referencing, please see
Referencing for beginners and
Citing sources. |
CRUVI is an expansion bus interface designed to create an open ecosystem of function modules for high-performance peripheral connectivity. Its main focus is on supporting FPGA and FPGA SoC devices from all major manufacturers like Intel ®, Lattice, Microchip and Xilinx.
The word "CRUVI" is a combination of the Estonian word "KRUVI" for screw and the letter "C", which refers to the half of the hexagonal screw head. In this case, the "K" was replaced with "C" to emphasize the reference to the screw head.
The CRUVI open standard coexists between low speed, low pin-count like Pmod Interface devices and high-performance, high pin-count ( HPC), 400 I/O FPGA Mezzanine Card (FMC) peripherals.
It can be used to build high performance prototypes, for system integration and testing to build complex systems from smaller building blocks to iterate quickly and reduce cost. Create custom test systems for production functional testing. It's a perfect platform for your next high-performance semiconductor evaluation boards and systems.
Interface bridging to or from other coexistence ecosystem is possible to do with peripheral modules or boards.
Three board-to-board connectors are specified: CRUVI-LS (Low Speed), CRUVI-HS (High Speed) and CRUVI-GT ( Gigabit Transceiver) PCIe Gen 5.0 capable.
Peripheral CRUVI-HS and CRUVI-GT test board with loopback, scope or logic analyzer functions can verify the i.e. high speed connector performance or to be probed signals. [1]
International contributors to define the open source CRUVI specification are Trenz Electronic GmbH, Arrow Electronics, Samtec, Flinders University, Synaptic Laboratories Ltd, Symbiotic EDA and MicroFPGA UG.
History of CRUVI open source specification – FREE to use Apache License 2.0
Year | Version | Notes | Refs |
---|---|---|---|
2021 | 1.0.7 -alpha | first release | [1] |
2024 | 2.0.1 -alpha | coming soon |
Carrier board or host board delivers power supplies, IO voltage and controls the functions of peripheral modules.
Single, double or triple width modules are allowed and they have more mounting holes.
A triple size of space on carrier board (PCB template CR99201) is 2.666 inches by 2.264 inches (67.72 mm × 57.5 mm) with LS and HS connectors. There are 3 slots named: AX, BY, and CZ. The mounting holes (1 to 6) for M2 screws are 2.2 mm (0.0866 inch) diameter and need SMD spacer for mechanically fixing. [1]
It is recommended for all FPGA host boards with CRUVI slots provide LiteX platform support files. [2]
Host and carrier boards are available with FPGA´s from Intel ® (TEI0050, TEI0185 [3], CR00010, CR00100, CR00109), Lattice (TEL003, CR00103), Microchip (TEMB0005) and Xilinx (TEBF0707, CR00107). [4]
Bridging adapter exists to convert signals from Pmod to CRUVI-LS (CR00025), from FMC to CRUVI-HS (CR00101, CR00111) and FMC to CRUVI-GT (CR00112). [1]
There are different single peripheral module possible, flexible and scalable by size LS, HS and GT connectors. Mounting holes are for M2 screws 2.2 millimeters (0.087 in) diameter.
It is recommended to have EEPROM with I2C for identification of peripheral module with a specific address number.
L × H | speed | PCB template [5] | Note |
---|---|---|---|
14 mm × 14 mm (0.55 in × 0.55 in) |
LS | CR99001 |
identification EEPROM is included; This template is usefull for I2C, I3C, SPI sensor, I2S PDM MEMS microphones, programmable oscillator, ADC, DAC or SPI (QSPI) Flash memory device in BGA24 or SO-8 package. |
14 mm × 14 mm (0.55 in × 0.55 in) |
LS | CR99002 | same as CR99001 with added u.Fl connectors for I/O |
22 mm × 32 mm (0.87 in × 1.26 in) |
LS | CR99003 |
maximum size one-wide half-length, identification EEPROM is included |
18 mm × 32 mm (0.71 in × 1.26 in) |
LS | CR99004 |
This template is useful to convert into Pmod compatible connector. |
22 mm × 30 mm (0.87 in × 1.18 in) |
LS | CR99005 |
is half-length LS module with two SMA connectors |
18 mm × 20 mm (0.71 in × 0.79 in) |
HS | CR99101 |
minimal size HS Module; good for HyperRAM or HyperFlash, eMMC or loopback adapter for CRUVI-HS |
22 mm × 57.5 mm (0.87 in × 2.26 in) |
HS | CR99102 |
maximum sized single-width HS module; good for signal test adapter to probed with scope or logic analyzer, for high speed interfaces like USB-C, HDMI, MIPI CSI/ DSI, SDIO, xGMII Ethernet and LVDS ADC (1 to 4 data lane) |
Connector | LS Low Speed | HS High Speed | GT Gigabit Transceiver |
---|---|---|---|
Carrier side connector | CLT-106-02-F-D-A-K | SS4-30-3.50-L-D-K | ADF6-20-03.5-L-4-2 |
Peripheral side connector | TMMH-106-04-F-DV-A-M | ST4-30-1.50-L-D-P | ADM6-20-01.5-L-4-2 |
Pin no | 12 (6 per row) | 60 (30 per row) | 80 (20 per row) |
pitch | 2 mm (0.079 in) | 0.4 mm (0.016 in) | 0.635 mm (0.0250 in) |
stacked height | 4.78 mm (0.188 in) to 5.29 mm (0.208 in) | 5 mm (0.20 in) | |
speed rating [GHz] / [Gbps] | 5.5 / 11 | 13.5 / 27 (single ended)
15.5 / 31 (differential) |
32 |
Single ended I/O pins (VCCIO) | 8 | 37 (28 adj.) + (9 fixed 3.3V) | 8 + I2C |
max. differential I/O | no | max. 12 LVDS | max. 4 lanes + REFCLK |
Power Supply | adj., 3.3V, 5V | ||
Current rating per pin [A] | 4.1 (2-pin powered) | 1.6 (2-pin powered) | 1.34 (4-pin powered) |
max. Temperatur range [°C] | −55 to 125 |
Pin | Primary | Signal | Pin | Primary | Signal |
---|---|---|---|---|---|
1 | SDA | I2C(SDA), SMBUS(SDA) | 7 | D1 | UART(RXD1), SD(D1), SPI(MISO), QSPI(D1), JTAG(TDI) |
2 | SCL | I2C(SCL), SMBUS(SCL) | 8 | CLK | UART(RTS), SD(CLK), SPI(CLK), QSPI(CLK), JTAG(TCK) |
3 | D3 | UART(RST), SD(TXD0), QSPI(D3), JTAG(nRST) | 9 | D0 | UART(TXD1), SD(D0), SPI(MOSI), QSPI(D0) JTAG(TDO) |
4 | SEL | UART(CTS), SD(CMD), SPI(SEL), QSPI(SEL), JTAG(TMS) | 10 | VCC | Power 3.3V |
5 | D2 | SMBUS(INT), UART(RXD0), SD(D2), QSPI(D2), JTAG(RFU) | 11 | RFU | tbd |
6 | GND | Ground | 12 | VBUS | Power 5V |
Pin | Primary Function | Note | Pin | Primary Function | Note | Pin | Primary Function | Note | Pin | Primary Function | Note |
---|---|---|---|---|---|---|---|---|---|---|---|
1 | RFU1 | 16 | A0_N | Transceiver I/O | 31 | GND | Ground | 46 | A5_N | Transceiver I/O | |
2 | HSIO | 17 | B0_N | Transceiver I/O | 32 | A3_P | 47 | B5_N | Transceiver I/O | ||
3 | ALERT/IRQ | 18 | GND | Ground | 33 | B3_P | Transceiver I/O | 48 | GND | Ground | |
4 | VCC | 3,3V | 19 | GND | Ground | 34 | A3_N | 49 | GND | Ground | |
5 | SDA | 20 | A1_P | Transceiver I/O | 35 | B3_N | Transceiver I/O | 50 | RFU2_P | ||
6 | HSO | 21 | B1_P | Transceiver I/O | 36 | VADJ | 1.2 to 3.3V | 51 | DI/TDI | JTAG, SPI(MISO) | |
7 | SCL | 22 | A1_N | Transceiver I/O | 37 | GND | Ground | 52 | RFU2_N | ||
8 | HSRST | 23 | B1_N | Transceiver I/O | 38 | A4_P | Transceiver I/O | 53 | DO/TDO | JTAG, SPI(MOSI) | |
9 | VCC | 3.3V | 24 | GND | Ground | 39 | B4_P | Transceiver I/O | 54 | GND | Ground |
10 | HSI | 25 | GND | Ground | 40 | A4_N | Transceiver I/O | 55 | SEL/TMS | JTAG, SPI(SEL) | |
11 | REFCLK | 26 | A2_P | 41 | B4_N | Transceiver I/O | 56 | RFU_P | |||
12 | GND | Ground | 27 | B2_P | Transceiver I/O | 42 | GND | Ground | 57 | MODE | JTAG EN |
13 | GND | Ground | 28 | A2_N | 43 | GND | Ground | 58 | RFU_N | ||
14 | A0_P | Transceiver I/O | 29 | B2_N | Transceiver I/O | 44 | A5_P | Transceiver I/O | 59 | SCK/TCK | JTAG, SPI(CLK) |
15 | B0_P | Transceiver I/O | 30 | GND | Ground | 45 | B5_P | Transceiver I/O | 60 | VBUS | 5V |