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From Wikipedia, the free encyclopedia
v
t
e
Hardware acceleration
Theory
Universal Turing machine
Parallel computing
Distributed computing
Applications
GPU
GPGPU
DirectX
Audio
Digital signal processing
Hardware random number generation
Artificial intelligence
Cryptography
TLS
Machine vision
Custom hardware attack
scrypt
Networking
Data
Implementations
High-level synthesis
C to HDL
FPGA
ASIC
CPLD
System on a chip
Network on a chip
Architectures
Dataflow
Transport triggered
Multicore
Manycore
Heterogeneous
In-memory computing
Systolic array
Neuromorphic
Related
Programmable logic
Processor
design
chronology
Digital electronics
Virtualization
Hardware emulation
Logic synthesis
Embedded systems
Template documentation
[
create
] [
purge
]
Editors can experiment in this template's sandbox
(
create
|
mirror
)
and testcases
(
create
)
pages.
Add categories to the
/doc
subpage.
Subpages of this template
.
Category
:
Computer hardware navigational boxes
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