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No Secure enclave processing instructions listed. — Preceding unsigned comment added by 100.6.80.179 ( talk) 01:04, 8 October 2018 (UTC)
wich instructions are integer, wich are floating point, wich are "other"? (similar distinction as in SSE/2/3 lists) Alinor 14:03, 25 February 2006 (UTC)
Some processors are not mentioned in the "instructions added with" lists:
"The i487 SX was not really a Co Processor. It was a normal i80486 DX processor when installed to disable the onboard SX Processor and take over main operation of the CPU and add an FPU. The i487 has one pin more than a normal 486 cpu, so you need a special socket to install this chip."</endblockquote>[ i80487sx ] 207.53.252.58 ( talk) 20:27, 17 July 2023 (UTC)
"The Pentium F00F bug is a design flaw in the majority of Intel Pentium, Pentium MMX, and Pentium OverDrive processors (all in the P5 micro architecture). Discovered in 1997, it can result in the processor ceasing to function until the computer is physically rebooted. The bug has been circumvented through operating system updates."
"In the
x86 architecture, the byte sequence F0 0F C7 C8
represents the instruction lock cmpxchg8b eax
(locked compare and exchange of 8 bytes in register EAX). The bug also applies to opcodes ending in C9
through CF
, which specify register
operands other than EAX. The F0 0F C7 C8
instruction does not require any
special privileges."
</endblockquote>[ Pentium F0 0F
/info/en/?search=Pentium_F00F_bug]
207.53.252.58 (
talk)
20:27, 17 July 2023 (UTC)
Maybe no new instructions are added with these CPUs, but does someone know for sure?
Also, there are some CPUs that are not mentioned in some particular lists, but this is OK, because they have not added new instructions there for sure:
Anyway it would be good to put (a) placeholder(s) for each of these CPUs with a "nothing added" mark, so that it is clear that the list is complete. Alinor 14:03, 25 February 2006 (UTC) Readablity edit JSo9-10 ( talk) 06:30, 17 June 2010 (UTC)
The Haswell chips have introduced new instructions also (MOVBE is one - it already is in the ATOM chips). It needs to be listed here also. Johnreagan ( talk) 18:02, 23 April 2013 (UTC)
there are many more x86 CPU manufacturers. Maybe some of them support some additional instructions. It would be good to at least add a section "Other x86 CPUs - list-stub": Chips and Technologies Super386, Cyrix 386/486/5x86/6x86/6x86MX, Cyrix/ NatSemi MediaGX/AMD Geode, VIA Cyrix C3, VIA Centaur C3, IDT Centaur, NEC V10/V20, Rise Technology mP6, SiS SoC, NexGen Nx586/Nx587/K6, Transmeta Cursoe/Efficeon, UMC Super486, SGS-Thomson/ IBM/ Texas Instruments/others generic manufacturers, ALi/ULi/other embedded designs.
I'd like to see this list have actual x86 instruction - like the MIPS page has. Like, with this list, you should be able to learn the assembly. Fresheneesz 18:41, 13 April 2006 (UTC)
Firstly, there is the 102 page (yes, I printed it out) appendix b of the NASM manual. Then there is Intel's documentation regarding the Pentium 4 and other specifications. I'm sure that the GNU assembler has some sort of helpful documentation as well, but I haven't checked.
Was CPUID introduced in the 486? This article says that it was, but I think it might have been introduced with the Pentium and not earlier. - Richardcavell 04:17, 3 January 2007 (UTC)
It is certainly not listed in programming manuals dated around the time. Specifically, "Using Assembly Language", which covers the 80486, has no mention of this instruction. —Preceding unsigned comment added by 92.232.150.252 ( talk) 20:26, 7 September 2009 (UTC)
I'm going to be converting the lists of instructions that aren't in table form (e.g. 486 instructions and up) and converting it into tables as a way to spend my summer. If you want to help with this or have any questions / comments, post them on my usertalk. Thanks!
Andreyvul (
talk)
07:23, 31 July 2008 (UTC)
Specifically, help with tabulating the floating-point instructions would be nice.
Andreyvul (
talk)
17:01, 31 July 2008 (UTC)
The instructions bswap,cmpxchg,invd,invlpg,wbinvd,xadd
Do they exist on the AMD K5 and AMD K6? What about on the Cyrix 686?
And the Pentium instructions: cmpxchg8b, rdmsr, rdtsc, wrmsr ...
Do they exist on the AMD K5 and AMD K6? What about on the Cyrix 686?
Mark Hobley —Preceding undated comment was added at 20:36, 8 February 2009 (UTC).
When you compile a program for a windows 32 bit system, which assembly language and which machine language is used? In other words, which of the instruction sets is it that is used in .exe-files? I can't find it in the article, maybe it could be put there? -- Kri ( talk) 23:49, 26 February 2009 (UTC)
This was broken out into a section for instructions added in the Pentium II. This is incorrect. The Pentium Pro instruction reference [1] lists it as available since the Pentium. I don't have a reference to the original Pentium manuals, but I see no reason to believe that it was not listed in those; certainly when I was working on NASM the instruction was well known, and I'm pretty certain it wasn't on our list as undocumented.
Even if it wasn't officially documented at the time, it has since been officially documented as available on the Pentium, so it belongs in the section for Pentium. I have moved it back. JulesH ( talk) 22:35, 28 March 2009 (UTC)
The 386 table lists LODSW as new. That should be deleted surely? As not "new" - was in the 8086? Check thatI'm not going mad, and feel free to correct the table, or I'll do it. 83.105.29.227 ( talk) 12:51, 1 June 2009 (UTC)
OR is linked to http://en.wikipedia.org/wiki/Logical_NOR instead of http://en.wikipedia.org/wiki/Logical_OR. As i'm pretty new to assembly, i won't change it but would like to have it checked by someone who knows what he's doing.
My first "PC" back in the '80s had an NEC V20, and the assorted paperwork that came with it said the exact opposite: The <evil> Intel 8088/86 didn't care what you put in the 2nd opcode because when the processor saw the primary opcode it read 0x0A regardless of what was actually in the byte stream, whereas the <good> NEC V20 would faithfully use whatever operand you put in there and thus was useful in a general-purpose baseshifting routine. This, they went on to explain, was a quick way to determine if a program was running on an Intel or NEC chip. Anyone here have a quick way to be sure which is correct? I do not have an operable 8088/86 _or_ V-series computer. SandyJax ( talk) 21:00, 24 January 2011 (UTC)
; Try for an NEC V20/30 mov ax, 0208h db 0D5h,16 ; Only the 8088 actually checks the arg to AAD cmp al, 28h ; as intel ran out of microcode space jz short cmos mov bx, 4 ; NEC V20 jmp short test8
For instance what is /r? WvvvvL01 69 /r /is4 say what? This stuff is not so easy to find out, and isn't generally covered in ASM manuals. PS: Not asking for help, just saying it's too opaque as is. -- 67.54.192.52 ( talk) 05:42, 3 February 2011 (UTC)
The presented information about the ENTER instruction (that it is equivalent to PUSH BP / MOV BP, SP / SUB SP, n) is correct only if the second operand (the nesting level) is zero. If it's non-sero, the behaviour of ENTER is more complex. See for example the Am186™ and Am188™ Family Instruction Set Manual (p. 4-53) for a description of this instruction.
Лъчезар☭共产主义万岁★ 15:17, 4 April 2011 (UTC)
The sections 1.2 ("Added in specific processors") and 2.2 ("Added in specific processors") state that the instructions listed in its sub-sections have been added with some processor, but they miss to describe what the basis for the addition was. Not in all cases is the addition relative to the previous section / processor. In most cases, it is not the base 8086/8087 instruction set, either.
These sections should be updated to explicitly state relative to which other section or processor the instructions listed in the current section were added.
Gandalf44 ( talk) 15:38, 11 May 2011 (UTC)
Section 1.2 ("Added in specific processors") describes SSEx as processors and lists certain instructions that were added. Section 3 ("SIMD instructions") describes SSEx as a set of instructions (which is correct). There are multiple issues with this approach:
I suggest that section 1.2 really only mentions instructions added by processors (or microarchitectures, as a means to refer to all the processors implementing that microarchitecture), and that specific named instruction sets are only described in section 3. If processor types need to be qualified because there are different flavors supporting different instruction sets, than such a qualification simply needs to be added.
Gandalf44 ( talk) 15:56, 11 May 2011 (UTC)
The instruction list shown in the table in section 3.6.2 ("SSE SIMD Integer Instructions") lists NOP with opcode 0F 1F. This is different from the NOP in the 8086 base instruction set (opcode 90). It would be helpful to explain why a different NOP was needed (if anyone knows ... - or at least to point out that this is a different opcode that shares the same mnemonic).
Gandalf44 ( talk) 16:52, 11 May 2011 (UTC)
This is about a multi-byte NOP. The "new NOP" accepts different addressing modes, allowing for different instruction sizes.
If you need 1 byte, you still have to use the old XCHG AX,AX NOP.
DiederikH (
talk)
19:30, 16 October 2012 (UTC)
I have made some tests with this (apparent) HCF opcode and I had to conclude the following:
The CPU is an Am286-16.
DiederikH ( talk) 17:19, 14 October 2012 (UTC)
I believe it would be useful to add AT&T mnemonics to help finding instructions such as movl/addl/etc, both to help search engine results and also when doing textual searches inside the page.
However, this could complicate a bit things, since for instance many such instructions (e.g. mov) are defined for 8086 on Intel syntax, but might have to be added under a different family for the "extended" version. — Preceding unsigned comment added by Dhekir ( talk • contribs) 07:25, 20 July 2015 (UTC)
Hello fellow Wikipedians,
I have just modified 2 external links on X86 instruction listings. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
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the page lacks 8A ** ** ** instruction, which is from 8086 or older and compatiblity is kept till today. I tried today to disassemble some program and it seems my disassembler also don't know it. here is some info, I don't fully understand: http://ref.x86asm.net/coder32.html#x8A — Preceding unsigned comment added by 89.74.199.35 ( talk) 02:12, 9 August 2016 (UTC)
according to http://aturing.umcs.maine.edu/~meadow/courses/cos335/8086-instformat.pdf "8a 86 d5" is mov al, D5 — Preceding unsigned comment added by 89.74.199.35 ( talk) 02:53, 9 August 2016 (UTC)
sorry it were new instruction "8a 86 d5 00 00 00" mov al, [esi + 0xd5] — Preceding unsigned comment added by 89.74.199.35 ( talk) 06:42, 9 August 2016 (UTC)
Is there a similar page for ARM listings? If not, then one could create by automating from the ARM documentation itself. Anyone up for it? — Preceding unsigned comment added by Temp00guy ( talk • contribs) 01:51, 29 April 2017 (UTC)
[[|thumb| https://hsto.org/webt/ph/4k/70/ph4k700mdvxwacaepm4uzqoq188.png]] from https://habr.com/ru/post/503486/ — Preceding unsigned comment added by Arkeke ( talk • contribs) 06:31, 24 November 2020 (UTC)
I would like an operands column in the table under integer instruction listings. I don't think the notes column would suffice. This text might not be sufficient, in that case, ask and I shall provide info. This may be unnecessary, in that case ignore this. — Preceding unsigned comment added by BigGayDinosaur ( talk • contribs) 04:56, 4 January 2021 (UTC)
Hey
User:Punpcklbw; I see you've been active on this article and I was wondering if you'd like to help me split it off into sublists which would help make the main article more accessible (which would also allow more space for references, context about prefixes and encoding, etc.) I'll propose a structure in a bit if you're interested. Love the username, by the way; had to use vpunpckl(hd)q
recently. :)
Ovinus (
talk)
03:46, 21 June 2022 (UTC)
punpcklbw xmm, xmm, xmm
[a]; pshufb xmmm, xmm
[b] My overall concept is: Order by instruction type, then by chronology, and finally split off less-important or very fat instruction sets. The article sort of does that already, although the header "x86 integer instructions" is a bit misleading—it's currently integer instructions and miscellaneous instructions, so maybe rename it to "general-purpose" (but I don't know how descriptive that is either). I'd say the first thing to do is to split off obsolete instructions like most of the stuff in "Added in specific non-Intel processors" into
List of nonstandard x86 instructions or
List of obsolete x86 instructions. I'd also move 3DNow! (excluding prefetch), MPX, EMMI, and maybe XOP since AMD isn't supporting it anymore. The rationale is that those instructions are just... not useful anymore, and the reader shouldn't have to wade through them. If they're really curious they can check the links, but I think presenting these random instruction sets in the same article as SSE is quite misleading.HLT
[c] and MOV ...
[d], and maybe alignment information for the handful of instructions which allow unaligned loads. In the table, do you think we should group scalar SSE instructions, e.g. MULSD xmm, xmm
, separately from vector instructions?1 0 2 4 34 3 1 0 2 4 3ndard" SSE pattern (FP32 vector with no prefix, FP32 scalar with F3h prefix, FP64 vector with 66h prefix, FP64 scalar with F2h prefix + the new AVX512-FP16 instructions) as well as indicators for AVX/AVX512 extensions of these instructions. My main concern was that such a table would become too impractically wide, however with a table now prepared - at [4] - it did get a bit unwieldy and visually noisy, but not nearly as much as I feared. Also, I've tried to add a few footnotes, and yes, it does seem to fit well with this kind of table approach.
vpermd
and vpermq
) and cross-lane byte permuting was added in AVX512 VBMI (vpermi2b {k}{z} zmm, zmm, zmm
).
{{
cite book}}
: CS1 maint: location missing publisher (
link)
[7]
This article was the subject of an educational assignment supported by
Wikipedia Ambassadors through the
India Education Program.
The above message was substituted from {{IEP assignment}}
by
PrimeBOT (
talk) on
20:01, 1 February 2023 (UTC)
![]() | This article was nominated for deletion on 30 June 2022. The result of the discussion was no consensus. |
![]() | This article is rated List-class on Wikipedia's
content assessment scale. It is of interest to the following WikiProjects: | ||||||||||||||||
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No Secure enclave processing instructions listed. — Preceding unsigned comment added by 100.6.80.179 ( talk) 01:04, 8 October 2018 (UTC)
wich instructions are integer, wich are floating point, wich are "other"? (similar distinction as in SSE/2/3 lists) Alinor 14:03, 25 February 2006 (UTC)
Some processors are not mentioned in the "instructions added with" lists:
"The i487 SX was not really a Co Processor. It was a normal i80486 DX processor when installed to disable the onboard SX Processor and take over main operation of the CPU and add an FPU. The i487 has one pin more than a normal 486 cpu, so you need a special socket to install this chip."</endblockquote>[ i80487sx ] 207.53.252.58 ( talk) 20:27, 17 July 2023 (UTC)
"The Pentium F00F bug is a design flaw in the majority of Intel Pentium, Pentium MMX, and Pentium OverDrive processors (all in the P5 micro architecture). Discovered in 1997, it can result in the processor ceasing to function until the computer is physically rebooted. The bug has been circumvented through operating system updates."
"In the
x86 architecture, the byte sequence F0 0F C7 C8
represents the instruction lock cmpxchg8b eax
(locked compare and exchange of 8 bytes in register EAX). The bug also applies to opcodes ending in C9
through CF
, which specify register
operands other than EAX. The F0 0F C7 C8
instruction does not require any
special privileges."
</endblockquote>[ Pentium F0 0F
/info/en/?search=Pentium_F00F_bug]
207.53.252.58 (
talk)
20:27, 17 July 2023 (UTC)
Maybe no new instructions are added with these CPUs, but does someone know for sure?
Also, there are some CPUs that are not mentioned in some particular lists, but this is OK, because they have not added new instructions there for sure:
Anyway it would be good to put (a) placeholder(s) for each of these CPUs with a "nothing added" mark, so that it is clear that the list is complete. Alinor 14:03, 25 February 2006 (UTC) Readablity edit JSo9-10 ( talk) 06:30, 17 June 2010 (UTC)
The Haswell chips have introduced new instructions also (MOVBE is one - it already is in the ATOM chips). It needs to be listed here also. Johnreagan ( talk) 18:02, 23 April 2013 (UTC)
there are many more x86 CPU manufacturers. Maybe some of them support some additional instructions. It would be good to at least add a section "Other x86 CPUs - list-stub": Chips and Technologies Super386, Cyrix 386/486/5x86/6x86/6x86MX, Cyrix/ NatSemi MediaGX/AMD Geode, VIA Cyrix C3, VIA Centaur C3, IDT Centaur, NEC V10/V20, Rise Technology mP6, SiS SoC, NexGen Nx586/Nx587/K6, Transmeta Cursoe/Efficeon, UMC Super486, SGS-Thomson/ IBM/ Texas Instruments/others generic manufacturers, ALi/ULi/other embedded designs.
I'd like to see this list have actual x86 instruction - like the MIPS page has. Like, with this list, you should be able to learn the assembly. Fresheneesz 18:41, 13 April 2006 (UTC)
Firstly, there is the 102 page (yes, I printed it out) appendix b of the NASM manual. Then there is Intel's documentation regarding the Pentium 4 and other specifications. I'm sure that the GNU assembler has some sort of helpful documentation as well, but I haven't checked.
Was CPUID introduced in the 486? This article says that it was, but I think it might have been introduced with the Pentium and not earlier. - Richardcavell 04:17, 3 January 2007 (UTC)
It is certainly not listed in programming manuals dated around the time. Specifically, "Using Assembly Language", which covers the 80486, has no mention of this instruction. —Preceding unsigned comment added by 92.232.150.252 ( talk) 20:26, 7 September 2009 (UTC)
I'm going to be converting the lists of instructions that aren't in table form (e.g. 486 instructions and up) and converting it into tables as a way to spend my summer. If you want to help with this or have any questions / comments, post them on my usertalk. Thanks!
Andreyvul (
talk)
07:23, 31 July 2008 (UTC)
Specifically, help with tabulating the floating-point instructions would be nice.
Andreyvul (
talk)
17:01, 31 July 2008 (UTC)
The instructions bswap,cmpxchg,invd,invlpg,wbinvd,xadd
Do they exist on the AMD K5 and AMD K6? What about on the Cyrix 686?
And the Pentium instructions: cmpxchg8b, rdmsr, rdtsc, wrmsr ...
Do they exist on the AMD K5 and AMD K6? What about on the Cyrix 686?
Mark Hobley —Preceding undated comment was added at 20:36, 8 February 2009 (UTC).
When you compile a program for a windows 32 bit system, which assembly language and which machine language is used? In other words, which of the instruction sets is it that is used in .exe-files? I can't find it in the article, maybe it could be put there? -- Kri ( talk) 23:49, 26 February 2009 (UTC)
This was broken out into a section for instructions added in the Pentium II. This is incorrect. The Pentium Pro instruction reference [1] lists it as available since the Pentium. I don't have a reference to the original Pentium manuals, but I see no reason to believe that it was not listed in those; certainly when I was working on NASM the instruction was well known, and I'm pretty certain it wasn't on our list as undocumented.
Even if it wasn't officially documented at the time, it has since been officially documented as available on the Pentium, so it belongs in the section for Pentium. I have moved it back. JulesH ( talk) 22:35, 28 March 2009 (UTC)
The 386 table lists LODSW as new. That should be deleted surely? As not "new" - was in the 8086? Check thatI'm not going mad, and feel free to correct the table, or I'll do it. 83.105.29.227 ( talk) 12:51, 1 June 2009 (UTC)
OR is linked to http://en.wikipedia.org/wiki/Logical_NOR instead of http://en.wikipedia.org/wiki/Logical_OR. As i'm pretty new to assembly, i won't change it but would like to have it checked by someone who knows what he's doing.
My first "PC" back in the '80s had an NEC V20, and the assorted paperwork that came with it said the exact opposite: The <evil> Intel 8088/86 didn't care what you put in the 2nd opcode because when the processor saw the primary opcode it read 0x0A regardless of what was actually in the byte stream, whereas the <good> NEC V20 would faithfully use whatever operand you put in there and thus was useful in a general-purpose baseshifting routine. This, they went on to explain, was a quick way to determine if a program was running on an Intel or NEC chip. Anyone here have a quick way to be sure which is correct? I do not have an operable 8088/86 _or_ V-series computer. SandyJax ( talk) 21:00, 24 January 2011 (UTC)
; Try for an NEC V20/30 mov ax, 0208h db 0D5h,16 ; Only the 8088 actually checks the arg to AAD cmp al, 28h ; as intel ran out of microcode space jz short cmos mov bx, 4 ; NEC V20 jmp short test8
For instance what is /r? WvvvvL01 69 /r /is4 say what? This stuff is not so easy to find out, and isn't generally covered in ASM manuals. PS: Not asking for help, just saying it's too opaque as is. -- 67.54.192.52 ( talk) 05:42, 3 February 2011 (UTC)
The presented information about the ENTER instruction (that it is equivalent to PUSH BP / MOV BP, SP / SUB SP, n) is correct only if the second operand (the nesting level) is zero. If it's non-sero, the behaviour of ENTER is more complex. See for example the Am186™ and Am188™ Family Instruction Set Manual (p. 4-53) for a description of this instruction.
Лъчезар☭共产主义万岁★ 15:17, 4 April 2011 (UTC)
The sections 1.2 ("Added in specific processors") and 2.2 ("Added in specific processors") state that the instructions listed in its sub-sections have been added with some processor, but they miss to describe what the basis for the addition was. Not in all cases is the addition relative to the previous section / processor. In most cases, it is not the base 8086/8087 instruction set, either.
These sections should be updated to explicitly state relative to which other section or processor the instructions listed in the current section were added.
Gandalf44 ( talk) 15:38, 11 May 2011 (UTC)
Section 1.2 ("Added in specific processors") describes SSEx as processors and lists certain instructions that were added. Section 3 ("SIMD instructions") describes SSEx as a set of instructions (which is correct). There are multiple issues with this approach:
I suggest that section 1.2 really only mentions instructions added by processors (or microarchitectures, as a means to refer to all the processors implementing that microarchitecture), and that specific named instruction sets are only described in section 3. If processor types need to be qualified because there are different flavors supporting different instruction sets, than such a qualification simply needs to be added.
Gandalf44 ( talk) 15:56, 11 May 2011 (UTC)
The instruction list shown in the table in section 3.6.2 ("SSE SIMD Integer Instructions") lists NOP with opcode 0F 1F. This is different from the NOP in the 8086 base instruction set (opcode 90). It would be helpful to explain why a different NOP was needed (if anyone knows ... - or at least to point out that this is a different opcode that shares the same mnemonic).
Gandalf44 ( talk) 16:52, 11 May 2011 (UTC)
This is about a multi-byte NOP. The "new NOP" accepts different addressing modes, allowing for different instruction sizes.
If you need 1 byte, you still have to use the old XCHG AX,AX NOP.
DiederikH (
talk)
19:30, 16 October 2012 (UTC)
I have made some tests with this (apparent) HCF opcode and I had to conclude the following:
The CPU is an Am286-16.
DiederikH ( talk) 17:19, 14 October 2012 (UTC)
I believe it would be useful to add AT&T mnemonics to help finding instructions such as movl/addl/etc, both to help search engine results and also when doing textual searches inside the page.
However, this could complicate a bit things, since for instance many such instructions (e.g. mov) are defined for 8086 on Intel syntax, but might have to be added under a different family for the "extended" version. — Preceding unsigned comment added by Dhekir ( talk • contribs) 07:25, 20 July 2015 (UTC)
Hello fellow Wikipedians,
I have just modified 2 external links on X86 instruction listings. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
When you have finished reviewing my changes, please set the checked parameter below to true or failed to let others know (documentation at {{
Sourcecheck}}
).
This message was posted before February 2018.
After February 2018, "External links modified" talk page sections are no longer generated or monitored by InternetArchiveBot. No special action is required regarding these talk page notices, other than
regular verification using the archive tool instructions below. Editors
have permission to delete these "External links modified" talk page sections if they want to de-clutter talk pages, but see the
RfC before doing mass systematic removals. This message is updated dynamically through the template {{
source check}}
(last update: 5 June 2024).
Cheers.— InternetArchiveBot ( Report bug) 13:36, 21 July 2016 (UTC)
the page lacks 8A ** ** ** instruction, which is from 8086 or older and compatiblity is kept till today. I tried today to disassemble some program and it seems my disassembler also don't know it. here is some info, I don't fully understand: http://ref.x86asm.net/coder32.html#x8A — Preceding unsigned comment added by 89.74.199.35 ( talk) 02:12, 9 August 2016 (UTC)
according to http://aturing.umcs.maine.edu/~meadow/courses/cos335/8086-instformat.pdf "8a 86 d5" is mov al, D5 — Preceding unsigned comment added by 89.74.199.35 ( talk) 02:53, 9 August 2016 (UTC)
sorry it were new instruction "8a 86 d5 00 00 00" mov al, [esi + 0xd5] — Preceding unsigned comment added by 89.74.199.35 ( talk) 06:42, 9 August 2016 (UTC)
Is there a similar page for ARM listings? If not, then one could create by automating from the ARM documentation itself. Anyone up for it? — Preceding unsigned comment added by Temp00guy ( talk • contribs) 01:51, 29 April 2017 (UTC)
[[|thumb| https://hsto.org/webt/ph/4k/70/ph4k700mdvxwacaepm4uzqoq188.png]] from https://habr.com/ru/post/503486/ — Preceding unsigned comment added by Arkeke ( talk • contribs) 06:31, 24 November 2020 (UTC)
I would like an operands column in the table under integer instruction listings. I don't think the notes column would suffice. This text might not be sufficient, in that case, ask and I shall provide info. This may be unnecessary, in that case ignore this. — Preceding unsigned comment added by BigGayDinosaur ( talk • contribs) 04:56, 4 January 2021 (UTC)
Hey
User:Punpcklbw; I see you've been active on this article and I was wondering if you'd like to help me split it off into sublists which would help make the main article more accessible (which would also allow more space for references, context about prefixes and encoding, etc.) I'll propose a structure in a bit if you're interested. Love the username, by the way; had to use vpunpckl(hd)q
recently. :)
Ovinus (
talk)
03:46, 21 June 2022 (UTC)
punpcklbw xmm, xmm, xmm
[a]; pshufb xmmm, xmm
[b] My overall concept is: Order by instruction type, then by chronology, and finally split off less-important or very fat instruction sets. The article sort of does that already, although the header "x86 integer instructions" is a bit misleading—it's currently integer instructions and miscellaneous instructions, so maybe rename it to "general-purpose" (but I don't know how descriptive that is either). I'd say the first thing to do is to split off obsolete instructions like most of the stuff in "Added in specific non-Intel processors" into
List of nonstandard x86 instructions or
List of obsolete x86 instructions. I'd also move 3DNow! (excluding prefetch), MPX, EMMI, and maybe XOP since AMD isn't supporting it anymore. The rationale is that those instructions are just... not useful anymore, and the reader shouldn't have to wade through them. If they're really curious they can check the links, but I think presenting these random instruction sets in the same article as SSE is quite misleading.HLT
[c] and MOV ...
[d], and maybe alignment information for the handful of instructions which allow unaligned loads. In the table, do you think we should group scalar SSE instructions, e.g. MULSD xmm, xmm
, separately from vector instructions?1 0 2 4 34 3 1 0 2 4 3ndard" SSE pattern (FP32 vector with no prefix, FP32 scalar with F3h prefix, FP64 vector with 66h prefix, FP64 scalar with F2h prefix + the new AVX512-FP16 instructions) as well as indicators for AVX/AVX512 extensions of these instructions. My main concern was that such a table would become too impractically wide, however with a table now prepared - at [4] - it did get a bit unwieldy and visually noisy, but not nearly as much as I feared. Also, I've tried to add a few footnotes, and yes, it does seem to fit well with this kind of table approach.
vpermd
and vpermq
) and cross-lane byte permuting was added in AVX512 VBMI (vpermi2b {k}{z} zmm, zmm, zmm
).
{{
cite book}}
: CS1 maint: location missing publisher (
link)
[7]
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