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John D. McCalpin, Ph.D. 16:58, 10 February 2007 (UTC)
Not a lot is known about the subject, as most information is from press releases (hence the stub branding). Once more information is known, it will be added.
Yes, the first goal of Torrenza is to plug a co-processor in a HTX slot and then communicate with CPU using HyperTransport. However, Torrenza is also a technology that incorporate co-processors into one single CPU package. Please see the slides from speakers at the AMD Technology Analyst Day [3]. -- 202.71.240.18 06:43, 25 July 2006 (UTC)
First, according to Tom Yager at InfoWorld, Torrenza is code name for the Next Gen platform (which you may already have assumed from reading the article). However, Barcelona, which is to be released mid-2007, is said to be the first chip from this intiative. [4]. It's been said (possibly wrongly) that Barcelona comes under K8L, but this was the Turion 64. [5]
So assuming this is all true, the article needs to be updated, along with the inaccurate article currently called K8L. In terms of the first chip to come from the Torrenza intiative, Barcelona, there's a lot of current information. According to reports, it's to be 40% than Cloverton, and will be released mid-2007 [6]. Further, it's supposed to have 128 bit wide SSE, be 80% faster in floating point over Opteron, offer new VM and power management techniques. Dedicated L2 cache per core, and a L3 cache [7]. So, again, this is the biggest revamp since 2003. The first L3, and 65nm process for AMD [8]. Nja247 ( talk • contribs) 13:02, 11 February 2007 (UTC)
Tom Yager's article at Infoworld uses the label Torrenza incorrectly. The revisions I made to the article on 10 February 2007 provide an accurate and (hopefully) clear explanation of what 'Torrenza' means. This can be easily verified by reviewing AMD's public web sites and presentations linked to from the main article. John D. McCalpin, Ph.D. 16:58, 17 February 2007 (UTC)
Quote: "It is rumoured that the future IBM POWER7 processors are socket compatible with Opteron processors"
What does this have to do with anything related to Torrenza? It's very out of place there and it looks like something that'd belong to POWER7's article or possibly Opteron's, but its relation to Torrenza seems non-existent. -- M.A. ( talk) 09:57, 15 May 2008 (UTC)
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To anyone who edits this page, I have the following information. The Torrenza program was started because of my work (see https://docs.google.com/presentation/d/1azrWvRj-xehnWt2vkA_6rA4Jo-a3wE0uGgbE5liU_dI/edit?usp=sharing). A few weeks after the Opteron came out I figured out that I could put an FPGA in one of the Opteron sockets. I got in touch with Peter Robinson in the Boston HPC center and said I wanted to do this. I then raised money, moved to San Jose and built a small board that put an FPGA into an Opteron socket. Two years later we got in touch with Peter again (who came out to visit us) and he kept telling me "you're not the only smart guy to wants to do this" Third time he said it I said "was it a company called Virtual Computer Corporation from Reseda?". He scrambled to his laptop opened his email and confirmed the letter was from me. He said "I guess I'll stop saying that". Then someone internal to AMD passed a letter around to the top executives with the title "Should we help these socket stealers?" The answer was yes and they created the Torrenza program. The program went on for many years. In the meantime Intel came to me and asked if I could do the same for Intel parts. I said "I need your top secret information on your bus". They gave me the data sheets for their front side bus. I concluded that this was indeed possible but they would have to bin out parts that could make the timing so they went directly to Xilinx. Intel then came up with a similar program because customers kept asking how Intel was going to respond to the FPGA in the socket technology that I had come up with (and patented). In the end AMD was going to shut down the program but I convinced Jay Owen that they shouldn't officially cancel the program because they had Intel spending lots of money on it. Steve Casselman 10/4/2020. — Preceding unsigned comment added by 50.45.170.57 ( talk) 09:30, 4 October 2020 (UTC)
This is the
talk page for discussing improvements to the
Torrenza article. This is not a forum for general discussion of the article's subject. |
Article policies
|
Find sources: Google ( books · news · scholar · free images · WP refs) · FENS · JSTOR · TWL |
![]() | This article has not yet been rated on Wikipedia's content assessment scale. |
|
John D. McCalpin, Ph.D. 16:58, 10 February 2007 (UTC)
Not a lot is known about the subject, as most information is from press releases (hence the stub branding). Once more information is known, it will be added.
Yes, the first goal of Torrenza is to plug a co-processor in a HTX slot and then communicate with CPU using HyperTransport. However, Torrenza is also a technology that incorporate co-processors into one single CPU package. Please see the slides from speakers at the AMD Technology Analyst Day [3]. -- 202.71.240.18 06:43, 25 July 2006 (UTC)
First, according to Tom Yager at InfoWorld, Torrenza is code name for the Next Gen platform (which you may already have assumed from reading the article). However, Barcelona, which is to be released mid-2007, is said to be the first chip from this intiative. [4]. It's been said (possibly wrongly) that Barcelona comes under K8L, but this was the Turion 64. [5]
So assuming this is all true, the article needs to be updated, along with the inaccurate article currently called K8L. In terms of the first chip to come from the Torrenza intiative, Barcelona, there's a lot of current information. According to reports, it's to be 40% than Cloverton, and will be released mid-2007 [6]. Further, it's supposed to have 128 bit wide SSE, be 80% faster in floating point over Opteron, offer new VM and power management techniques. Dedicated L2 cache per core, and a L3 cache [7]. So, again, this is the biggest revamp since 2003. The first L3, and 65nm process for AMD [8]. Nja247 ( talk • contribs) 13:02, 11 February 2007 (UTC)
Tom Yager's article at Infoworld uses the label Torrenza incorrectly. The revisions I made to the article on 10 February 2007 provide an accurate and (hopefully) clear explanation of what 'Torrenza' means. This can be easily verified by reviewing AMD's public web sites and presentations linked to from the main article. John D. McCalpin, Ph.D. 16:58, 17 February 2007 (UTC)
Quote: "It is rumoured that the future IBM POWER7 processors are socket compatible with Opteron processors"
What does this have to do with anything related to Torrenza? It's very out of place there and it looks like something that'd belong to POWER7's article or possibly Opteron's, but its relation to Torrenza seems non-existent. -- M.A. ( talk) 09:57, 15 May 2008 (UTC)
Hello fellow Wikipedians,
I have just modified one external link on Torrenza. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.
This message was posted before February 2018.
After February 2018, "External links modified" talk page sections are no longer generated or monitored by InternetArchiveBot. No special action is required regarding these talk page notices, other than
regular verification using the archive tool instructions below. Editors
have permission to delete these "External links modified" talk page sections if they want to de-clutter talk pages, but see the
RfC before doing mass systematic removals. This message is updated dynamically through the template {{
source check}}
(last update: 5 June 2024).
Cheers.— InternetArchiveBot ( Report bug) 09:16, 30 December 2016 (UTC)
To anyone who edits this page, I have the following information. The Torrenza program was started because of my work (see https://docs.google.com/presentation/d/1azrWvRj-xehnWt2vkA_6rA4Jo-a3wE0uGgbE5liU_dI/edit?usp=sharing). A few weeks after the Opteron came out I figured out that I could put an FPGA in one of the Opteron sockets. I got in touch with Peter Robinson in the Boston HPC center and said I wanted to do this. I then raised money, moved to San Jose and built a small board that put an FPGA into an Opteron socket. Two years later we got in touch with Peter again (who came out to visit us) and he kept telling me "you're not the only smart guy to wants to do this" Third time he said it I said "was it a company called Virtual Computer Corporation from Reseda?". He scrambled to his laptop opened his email and confirmed the letter was from me. He said "I guess I'll stop saying that". Then someone internal to AMD passed a letter around to the top executives with the title "Should we help these socket stealers?" The answer was yes and they created the Torrenza program. The program went on for many years. In the meantime Intel came to me and asked if I could do the same for Intel parts. I said "I need your top secret information on your bus". They gave me the data sheets for their front side bus. I concluded that this was indeed possible but they would have to bin out parts that could make the timing so they went directly to Xilinx. Intel then came up with a similar program because customers kept asking how Intel was going to respond to the FPGA in the socket technology that I had come up with (and patented). In the end AMD was going to shut down the program but I convinced Jay Owen that they shouldn't officially cancel the program because they had Intel spending lots of money on it. Steve Casselman 10/4/2020. — Preceding unsigned comment added by 50.45.170.57 ( talk) 09:30, 4 October 2020 (UTC)