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mmap call which is used for memory-mapped files works this way. Is this really the same principle?
Yes and no. All files are accessed via the data channel management, which optimally determines if the file should be fully buffered into RAM, accessed by the disk i/o controllers, or a combination of the two. This management of data resources is global, not by application or user, and dynamically being balanced continuously.
How exactly is this distinguished from the (today) standard paged virtual memory system, as seen from a user process viewpoint? -- ssd ( talk) 04:12, 6 June 2013 (UTC)
There is a curious drawback to single-level store architecture, which was observed in practice at some of the very largest "beige box" a.k.a. CISC CPU AS/400 systems. Their total amount of 48-bit storage addresses was large but finite and in case of constant heavy system workload, it got filled up to 100% in app. 1.5 years of uptime, causing a halt and necessitating a reboot to return to work. IBM didn't anticipate that customers would treat the AS/400 as a "quasi mainframe" or "affordable Tandem Himalaya" and try to run it for 24 x 7 x Aeons (even neglecting the application of six-monthly OS/400 minor release updates, which would have guaranteed reboots at regular intervals, including the re-initialization of address space). When black-cased RISC CPU AS/400 systems arrived the address space was extended from 48 to 64 bits, which practically eliminated this problem. 158.88.16.2 ( talk) 15:43, 29 August 2022 (UTC)
![]() | This article has not yet been rated on Wikipedia's
content assessment scale. It is of interest to the following WikiProjects: | ||||||||||
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mmap call which is used for memory-mapped files works this way. Is this really the same principle?
Yes and no. All files are accessed via the data channel management, which optimally determines if the file should be fully buffered into RAM, accessed by the disk i/o controllers, or a combination of the two. This management of data resources is global, not by application or user, and dynamically being balanced continuously.
How exactly is this distinguished from the (today) standard paged virtual memory system, as seen from a user process viewpoint? -- ssd ( talk) 04:12, 6 June 2013 (UTC)
There is a curious drawback to single-level store architecture, which was observed in practice at some of the very largest "beige box" a.k.a. CISC CPU AS/400 systems. Their total amount of 48-bit storage addresses was large but finite and in case of constant heavy system workload, it got filled up to 100% in app. 1.5 years of uptime, causing a halt and necessitating a reboot to return to work. IBM didn't anticipate that customers would treat the AS/400 as a "quasi mainframe" or "affordable Tandem Himalaya" and try to run it for 24 x 7 x Aeons (even neglecting the application of six-monthly OS/400 minor release updates, which would have guaranteed reboots at regular intervals, including the re-initialization of address space). When black-cased RISC CPU AS/400 systems arrived the address space was extended from 48 to 64 bits, which practically eliminated this problem. 158.88.16.2 ( talk) 15:43, 29 August 2022 (UTC)