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![]() | The contents of the Power estimation techniques for RTL page were merged into Register-transfer level on 14 October 2017. For the contribution history and old versions of the redirected page, please see its history; for the discussion at that location, see its talk page. |
If RTL-level design was ever used for RTL-logic design, and we could find a source to that effect, there might be a reason to imagine a relationship. But TTL and ECL and CMOS are more likely targets for it, and they're not linked, to let's not link the Resistor–transistor logic that's related only by initialism. Same from the other side(s). Dicklyon ( talk) 02:29, 24 April 2008 (UTC)
Thanks, -- Abdull ( talk) 23:17, 8 February 2010 (UTC)
The article says "...changes its state on each clock edge.". Shouldn't this be "...each rising clock edge." or "...each positive clock edge"? Ellingd ( talk) 16:53, 2 March 2010 (UTC)
D latch operation: at the edge of a clock, input will be made available at the output. The example, however implies that the input function is synchronised.
Wrong
process(clk)
begin
if rising_edge(clk) then
D <= not Q;
end if;
end process;
Right
D <= not Q;
process(clk)
begin
if rising_edge(clk) then
Q <= D;
end if;
end process;
-- Armandas j ( talk) 15:11, 15 April 2010 (UTC)
"Power estimation" would make a good addition to this existing RTL page, would improve the sources for this topic, and neither page is big enough that a spinoff is necessary. — {{U|
Technical 13}} (
e •
t •
c)
14:24, 22 April 2015 (UTC)
![]() | This article is rated C-class on Wikipedia's
content assessment scale. It is of interest to the following WikiProjects: | |||||||||||||||||||||||
|
![]() | The contents of the Power estimation techniques for RTL page were merged into Register-transfer level on 14 October 2017. For the contribution history and old versions of the redirected page, please see its history; for the discussion at that location, see its talk page. |
If RTL-level design was ever used for RTL-logic design, and we could find a source to that effect, there might be a reason to imagine a relationship. But TTL and ECL and CMOS are more likely targets for it, and they're not linked, to let's not link the Resistor–transistor logic that's related only by initialism. Same from the other side(s). Dicklyon ( talk) 02:29, 24 April 2008 (UTC)
Thanks, -- Abdull ( talk) 23:17, 8 February 2010 (UTC)
The article says "...changes its state on each clock edge.". Shouldn't this be "...each rising clock edge." or "...each positive clock edge"? Ellingd ( talk) 16:53, 2 March 2010 (UTC)
D latch operation: at the edge of a clock, input will be made available at the output. The example, however implies that the input function is synchronised.
Wrong
process(clk)
begin
if rising_edge(clk) then
D <= not Q;
end if;
end process;
Right
D <= not Q;
process(clk)
begin
if rising_edge(clk) then
Q <= D;
end if;
end process;
-- Armandas j ( talk) 15:11, 15 April 2010 (UTC)
"Power estimation" would make a good addition to this existing RTL page, would improve the sources for this topic, and neither page is big enough that a spinoff is necessary. — {{U|
Technical 13}} (
e •
t •
c)
14:24, 22 April 2015 (UTC)