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I see that in the two ends of the range indicated for the FSB speed, the first end is expresed in MHz (MegaHertz i.e. millions of cycles per second) and the second one in GT/s (GigaTransfers per second). The two units are not the same and have not the same meaning. Hz is a unit used for referring to cycles per second, and since in one single cycle there can be more than one transfers (e.g. this is the case for DDR SDRAM memory), I deem this way of expressing figures for the same item could be misleading. Corrado72 ( talk) 18:18, 8 December 2021 (UTC)
The Itanium processor was developed at Digital Equipment Corp. in the late '80s. DEC was acquired by Compaq in 1998, which in turn was acquired by HP in 2002. So Hewlett Packard acquired, but did not develop the Itanium processor. The article does not mention DEC at all and should. — Preceding unsigned comment added by Mberman54 ( talk • contribs) 11:53, 6 February 2017 (UTC)
Let's put everything into one timeline...
So it is chronologically impossible for anything done at DEC to have been available to HP/Intel for Itanium development. Nothing from DEC was available to HP until the same year that Merced shipped. ...unless somebody working for DEC leaked the information to HP/Intel, but there's not a hint of VLIW/EPIC in Alpha, nor in (as far as I can find) the four RISC projects at DEC that preceded Alpha. So where's the evidence?
Is it possible that DEC did "early research on EPIC/VLIW" that didn't end up in Itanium? (or Alpha?) Well, it's not physically IMpossible... but given that there's no sign of EPIC/VLIW in Alpha, then if such research existed they must have considered it a dead end. There is no indication of anything like this in the Alpha Architecture book. Nor in the papers from DECUS Symposia back when DEC was hinting at those pre-Alpha RISC processors, or the Alpha itself.
Much more likely is that you've heard about "Epicode", which was part of the Prism architecture. But this had nothing to do with "explicitly parallel" anything. Rather, "Epicode" stood for "extended processor instruction code". This was basically writeable control store in the CPU that defined "extended instructions" and could be loaded via a maintenance operation (somewhat like updating motherboard firmware). This allowed the instruction set to be extended in ways required for a particular OS, and allowed the extended instructions to be implemented in different ways on different models of CPU while presenting the same semantics to the OS. (On my Alpha PC/150 I had to reload the PALcode when changing between VMS and Windows NT.) Alpha included this concept but renamed it " PALcode" (Privileged Architecture Library code). Given the timeline it's even possible that DEC heard of "EPIC" being worked on by HP/Intel and changed their name from Epicode to PALcode to avoid confusion. Jeh ( talk) 20:37, 8 February 2017 (UTC)
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Per Microsoft's lifecycle page, here, Windows Server 2008 R2 for Itanium-Based Systems has a note that says "See the latest Service Pack listing for this product for the end of support dates." The last service pack's end of life date is 1/14/2020, so this would imply that Itanium *is* still supported until 2020. That change shouldn't be reverted unless there is some (recent) article stating otherwise. The blog from 2010 is outdated. — Preceding unsigned comment added by S-1-5-7 ( talk • contribs) 04:57, 8 April 2018 (UTC)
From MOS:TENSE, events are past tense: designed, sold, manufactured, etc. Even though they stopped selling them, all the existing ones don't disappear. And even if they did, the design still exists. Since this article covers all the different models, and even all the instances (chips) of that model, it can still exist, even if none are still around. Shakespeare's plays still exist, even though he died, and are present tense. The actual example in MOS:TENSE came not so many years ago, when I was sitting next to a running PDP-10 and noticed that it was in past tense. Like Itanium, PDP-10 is a processor design, though there are still machines in that exist, and (at least before Covid-19) were still running. The VMS hobbyist program recent stopped supporting VAX, but still supports Alpha and Itanium. Sorry to hear about Linux. Gah4 ( talk) 22:56, 29 July 2021 (UTC)
This is the
talk page for discussing improvements to the
Itanium article. This is not a forum for general discussion of the article's subject. |
Article policies
|
Find sources: Google ( books · news · scholar · free images · WP refs) · FENS · JSTOR · TWL |
![]() | Itanium has been listed as one of the Engineering and technology good articles under the good article criteria. If you can improve it further, please do so. If it no longer meets these criteria, you can reassess it. | |||||||||||||||
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Current status: Good article |
![]() | This article is rated GA-class on Wikipedia's
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|
This page has archives. Sections older than 60 days may be automatically archived by Lowercase sigmabot III when more than 4 sections are present. |
I see that in the two ends of the range indicated for the FSB speed, the first end is expresed in MHz (MegaHertz i.e. millions of cycles per second) and the second one in GT/s (GigaTransfers per second). The two units are not the same and have not the same meaning. Hz is a unit used for referring to cycles per second, and since in one single cycle there can be more than one transfers (e.g. this is the case for DDR SDRAM memory), I deem this way of expressing figures for the same item could be misleading. Corrado72 ( talk) 18:18, 8 December 2021 (UTC)
The Itanium processor was developed at Digital Equipment Corp. in the late '80s. DEC was acquired by Compaq in 1998, which in turn was acquired by HP in 2002. So Hewlett Packard acquired, but did not develop the Itanium processor. The article does not mention DEC at all and should. — Preceding unsigned comment added by Mberman54 ( talk • contribs) 11:53, 6 February 2017 (UTC)
Let's put everything into one timeline...
So it is chronologically impossible for anything done at DEC to have been available to HP/Intel for Itanium development. Nothing from DEC was available to HP until the same year that Merced shipped. ...unless somebody working for DEC leaked the information to HP/Intel, but there's not a hint of VLIW/EPIC in Alpha, nor in (as far as I can find) the four RISC projects at DEC that preceded Alpha. So where's the evidence?
Is it possible that DEC did "early research on EPIC/VLIW" that didn't end up in Itanium? (or Alpha?) Well, it's not physically IMpossible... but given that there's no sign of EPIC/VLIW in Alpha, then if such research existed they must have considered it a dead end. There is no indication of anything like this in the Alpha Architecture book. Nor in the papers from DECUS Symposia back when DEC was hinting at those pre-Alpha RISC processors, or the Alpha itself.
Much more likely is that you've heard about "Epicode", which was part of the Prism architecture. But this had nothing to do with "explicitly parallel" anything. Rather, "Epicode" stood for "extended processor instruction code". This was basically writeable control store in the CPU that defined "extended instructions" and could be loaded via a maintenance operation (somewhat like updating motherboard firmware). This allowed the instruction set to be extended in ways required for a particular OS, and allowed the extended instructions to be implemented in different ways on different models of CPU while presenting the same semantics to the OS. (On my Alpha PC/150 I had to reload the PALcode when changing between VMS and Windows NT.) Alpha included this concept but renamed it " PALcode" (Privileged Architecture Library code). Given the timeline it's even possible that DEC heard of "EPIC" being worked on by HP/Intel and changed their name from Epicode to PALcode to avoid confusion. Jeh ( talk) 20:37, 8 February 2017 (UTC)
Hello fellow Wikipedians,
I have just modified 13 external links on Itanium. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
{{
dead link}}
tag to
http://i.top500.org/stats/details/procgen/1299{{
dead link}}
tag to
http://www.hp.com/go/integrityWhen you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.
An editor has reviewed this edit and fixed any errors that were found.
Cheers.— InternetArchiveBot ( Report bug) 01:53, 18 November 2017 (UTC)
Per Microsoft's lifecycle page, here, Windows Server 2008 R2 for Itanium-Based Systems has a note that says "See the latest Service Pack listing for this product for the end of support dates." The last service pack's end of life date is 1/14/2020, so this would imply that Itanium *is* still supported until 2020. That change shouldn't be reverted unless there is some (recent) article stating otherwise. The blog from 2010 is outdated. — Preceding unsigned comment added by S-1-5-7 ( talk • contribs) 04:57, 8 April 2018 (UTC)
From MOS:TENSE, events are past tense: designed, sold, manufactured, etc. Even though they stopped selling them, all the existing ones don't disappear. And even if they did, the design still exists. Since this article covers all the different models, and even all the instances (chips) of that model, it can still exist, even if none are still around. Shakespeare's plays still exist, even though he died, and are present tense. The actual example in MOS:TENSE came not so many years ago, when I was sitting next to a running PDP-10 and noticed that it was in past tense. Like Itanium, PDP-10 is a processor design, though there are still machines in that exist, and (at least before Covid-19) were still running. The VMS hobbyist program recent stopped supporting VAX, but still supports Alpha and Itanium. Sorry to hear about Linux. Gah4 ( talk) 22:56, 29 July 2021 (UTC)