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Most of what I've done here doesn't need any explanation, but there's one correction I think warrants a note. I replaced every instance of "glass" with "oxide". This is because the silicon dioxide layer under a gate is not glass. Glass would not work. A glass is an amorphous solid - irregular arrangement of atoms. The common usage of "glass" happens to be an instance of this. SiO2 in MOSFETs is crystalline, not glass. -- Tim Starling
what does "whereas those to the left abstract from the body contact." mean? It doesn't make any sense to me, or at least is doesn't convey the indended meaning, in my mind. dave
I edited the terminals section. I didn't see any discussion about it on this page. All FET's have 4 terminals (except possibly JFETs, but I'm pretty sure they do. I'll check on this and add an exception if they don't). Most of the time they are connected internally because the body effect is only useful in a couple of cases and is detrimental in most others. There are times that it doesn't matter.
The internal connection is made for three reasons. The first is to simplify circuit design. Why have a 4th terminal come out of the package if it's just going to be connected to one of the others. The second is to reduce the cost of the package. A fourth terminal adds to cost and complexity of the package, especially since there are times that you want the body to be at a very different voltage then the source. The third reason is that there is some resistance to the leads and in some cases, such as high tempreature and high current use, that resistance can cause the small current running along the body lead and the large current running along the source lead to create a measurable differential between the body and source voltages. This causes a measurable amount of difference in the threashold voltage due to the body effect, which will cause irregular switching voltages in digital circuits and plays havoc with the gain in analog circuits. By making the connection internally the designer can help to negate those effects and keep the source and body as close in voltage as possible. High frequency switching can also bring the body effect into play because there is a measurable current flowing from the gate to the body due to the capacitance.
I can think of two, possibly three, times that one would want a seperate body connection. The first is in digital designs, where you can better control the switching characteristics by connecting the body of the N-channel to the GND and the body of the P-channel to Vdd because the source may be connected to another FET's drain. The second is in analog FET switches, where one takes an N-channel and connects its drain and source in parallel with a P-channel (Although in this case they are simple FET's, which don't have a drain or source. The parasitic diode of the FET is actually designed in). The body of the P-channel goes to Vdd and the N-channel to GND. The gate of the N-channel gets driven with a signal to Vdd and the P-channel gets driven with the N-channel signal inverted. As the N-channel gate goes high, the P-channel gate goes low. This design allow the passing of analog signals higher than Vdd and lower than GND. The only limit on amplitude is Vds max. The third I am not sure about because I can't remember if biasing the base seperately gave the FET better temp characteristics or worse. It was either to stabalize it or make it into a device capable of reading tempreatue. I'll look it up and maybe find a place for it on the MOSFET page. -- Jeffrobins
I believe the following statement is incorrect:
The drain and source may be doped of opposite type to the body, in the case of enhancement mode FETs, or doped of similar type to the body as in depletion mode FETs. Field-effect transistors are also distinguished by the method of insulation between body and gate. Types of FETs are:
To my understanding the drain and source are ALWAYS doped opposite that of the body/substrate, and it is the channel that connects drain to source that is either the same (enhancement type) or the opposite (depletion type) of the body/substrate. Trashmanal 17:54, 16 May 2007 (UTC)
Good catch. The channel at the surface near the gate is what is doped to be similar to the drain and source for depletion mode. It is often adjusted in both enhancement and depletion mode. Snafflekid 23:58, 16 May 2007 (UTC)
The schematic for your MOSFET shows a solid line connecting the Source and Drain. Does this not indicate a depletion mode MOSFET?. An enhancement mode MOSFET is symbolically shown with a dashed line between the Source and Drain.
The arrows for the 'metallurgical' contacts point at the bottom of the N diffusions. The metal contact is on the top surface. Shouldn't your arrows point to the upper surface of the N regions?.
IEEE: http://ewh.ieee.org/soc/es/Nov1998/14/education/
I'm planning on doing a lot of work on the MOSFET section. I hope to discuss how MOSFETs are evolving to smaller and smaller submicron dimensions, and the problems designers are encountering...obviously non-technically. I've created two subcategories I want to expand upon--why MOSFETs are so popular and the problems with scaling. Rmalloy 13:47, 14 Jul 2004 (UTC)
I think some work needs to be done in the introduction to MOSFET...most important part. for later. Rmalloy 18:38, 14 Jul 2004 (UTC)
IMHO the external link [1] is somewhat obscure - and I'm a member of that Yahoogroup! It's neither focused on FETs nor well known. I plan to remove the link when I have some better to provide. Pjacobi 19:26, 14 Jul 2004 (UTC)
I've added all I feel comfortable adding about MOSFETs in analog circuits. I wish someone could discuss analog stuff, since everything is so digital digital digital. Rmalloy 23:38, 14 Jul 2004 (UTC)
A quesiton: "The MOSFET's strengths as the workhorse transistor in most digital circuits does not translate into supremacy in analog circuits, in which the bipolar junction transistor (BJT) has traditionally been seen as the transistor of choice, due largely to its high gain." This does not seem correct, since FETs have near-infinite gain - essentially no current flows into the gate. Glengarry 21:09, 15 Jul 2004 (UTC)
each basic circuit needs an article. common source, common drain, common gate, source follower amplifiers, etc. i can, of course, draw schematics. but i don't know these well enough to do the articles. i can start them with what i know... same for BJTs. - Omegatron 16:00, Jan 19, 2005 (UTC)
I ve not heard this one before. So we can all now use BJTs instead of FETs to create a voltage controlled resistor. I dont think so! Statement needs modifying/removing cos its wrong. Light current 04:11, 17 August 2005 (UTC)
Are you guys saying that a bipolar transistor is a voltage-controlled device? That’s wrong they are current controlled. Small base current change gives large collector current change. The FET is a voltage-controlled device. Which I like using in my projects because they are the closest things to tubes, which I cut my wisdom teeth on in the late 60's early 70's. Inkdoe 13:22, 20 October 2005
What about MFET ? Magnetic Field effect transistors, and spintronic ?
moved from page;
" Field Effect Transistor (FET) patented in 1934 by Dr. Oskar Heil. Personally first read about the FET patent year in Analog Science Fiction Science Fact magazine in the late 70s early 80s in an article about hearing aides by Larry Niven or Jerry Pournelle."
The results of what exactly Nature suggested should be corrected is out... italicize each bullet point once you make the correction. -- user:zanimum
Near the top, the article says "depletion, in which a voltage applied decreases the current flow from source to drain." This isn't true, is it? I think whoever wrote that sentence was confusing the difference between n-channel and p-channel, with the difference between enhancement mode and depletion mode. It would be more accurate to say "enhancement mode, which is normally off, when zero voltage is applied, and depletion mode, which is normally on, when zero voltage is applied." Objections to this change? -- Monguin61 17:55, 4 March 2006 (UTC)
I was wondering what the difference between an NPN transistor used in TTL logic for example, and a(n) FET transistor?
Do they not both work by applying a small current to the base to all a current to pass through?
So what are the differences between the construction/operation of an NPN transistor and a(n) FET transistor?
This page didn't really give me much help on the construction of a(n) FET transistor, as from what I see it looks EXACTLY the same as an NPN transistor. And from what I can see it works the same way too, except somehow uses energy mostly when switching states instead of during. How is it that it uses less energy than an NPN transistor?
What are the main differences between a(n) FET transistor and an NPN transistor?
How is it that an NPN transistor uses up more energy than a(n) FET transistor?
How is it that a(n) FET transistor has to be used differently for logic gates than an NPN transistor?
Thanks so much for your help! -- TAz69x 23:50, 16 April 2006 (UTC)
I have recently been investigating the process by which a PIN diode can modulate a signal as a result of incident radiation. My main point of confusion has been my inability to find any mechanical diagrams of a PIN diode which operates through the presence of 3 terminals. Most of what I have read suggests that this is a strictly 2-terminal device (the PIN in question, a Hamamatsu S5971). I came across a diagram for a FET, and was struck by not only the presence of the proper number of terminals, but the drain signal's dependence on variations in the space charge region. I am mainly curious as to the possibility that my PIN may be closer in design to an FET, through the use of the intrinsic region as the source of the drain terminal. Whether this is may be a step in the proper direction or its equally likely counterpart, I would appreciate any insight that may be offered on the subject. Jmeyers 18:39, 10 May 2006 (UTC)
I don't know of any similarity between a PiN diode and a FET. A PIN diode is a two terminal device, operated in reverse bias. Light on the diode causes carrier generation which effectively looks like a leakage current proportional to the light on the PIN diode. Even a PN junction diode does this, the largish I (intrinsic) portion just increases the area where generation occurs making it more sensitive to light. Maybe the charge coupled device is what you have in mind as a three terminal device, or a phototransistor. Snafflekid 23:34, 10 May 2006 (UTC)
It costed 2 days of research, but i finally find out that the confusion in my head came from your description of the pinch-off mode. In your description you talk about the "saturation" area, where increasing source voltage you don't have corresponding increase of drain current and you call it pinch-off ... but still there is current and its value depend on the value of the gate voltage. While the pinch-off voltage is the value of the GATE voltage for which there is no drain current at all, for any value of source-to-drain voltage (even in the ohmic region!).
see reference: http://www.st-andrews.ac.uk/~jcgl/Scots_Guide/info/comp/active/jfet/jfetchar/jfetchar.htm
152.78.72.52 20:03, 3 February 2007 (UTC)
@ 2007-02-03T21:22Z
Ok... looking around for even longer i solved my doubts, i just want to leave the observation for others: the pinch off point is indeed what you describe. In particular, for Vgate=0 is the value of Vsource=Vpo when the saturation start (the channel is "almost close"). But on the other side if Vgate=Vpo, the channel is already almost close by the bias of the gate, so the drain current "saturate" soon, for very small value, and stay almost zero for any value of Vsource. That's why it can be seen in a transconductance graph as the value of Vgate for Idrain=0. Am I right?
This comment was added by ???
Is it possible to make an animation of a saturated FET opening, where the self-consistent potential is shown as the height and some electrons as spheres running over it. Drain and gate held at fixed potential and as the source potential rises, electrons spill over?
Arnero
05:15, 1 August 2007 (UTC)
like in static image Arnero 05:33, 1 August 2007 (UTC)
You won't get a good intuition for how devices work just from reading a Wikipedia article.
fixed potential and as the source potential rises, electrons spill over?
Something like this: http://jas.eng.buffalo.edu/education/semicon/diffusion/diffusion.html ? Anyhow, the "simulation" is to time consuming for me to code, and I did not find any tool in the web. And the animation would be pretty large. Arnero 11:19, 7 August 2007 (UTC)
I'd like seconding by someone more expert than myself before making any changes; The article says (Para 5 of section 'FET Operation'); "The shape of the inversion region becomes "pinched-off" near the drain end of the channel". Unless I am mistaken, when a positive potential difference is applied between D and S the pinch region is at the source end of the channel, as the potential difference pulls the charge carriers in the inversion region (the electrons) closer to the drain (positive potential). This is corroborated by my own knowledge as well as (not explicitly) here. Comments please, Spychotic ( talk)
This is not an error actually. Channel starts pinching off near Drain side first due to the voltage drop in the channel itself.-- Murat ( talk) 19:31, 22 November 2009 (UTC)
I keep seeing references to "FETs" as an ancient predecessor to MOSFETS et al described herein. What kind of FET is one referring to then? - 143.215.155.50 ( talk) 03:55, 10 October 2008 (UTC)
Why is there no FET history section? When and how was the FET created? - 143.215.155.50 ( talk) 03:55, 10 October 2008 (UTC)
There is a lack of information regarding the physics of channel inversion ... that is when the p type semiconductor has an n type channel formed under the gate. The statemant below is wrong.. the phenomenom is not called the threshold voltage, threshold is just the voltage at which this occurs and current begins conducting through the channel... the phenomenom is called inversion.
"..........; this forms a region free of mobile carriers called a depletion region, and the phenomenon is referred to as the threshold voltage of the FET. " —Preceding unsigned comment added by Jonnic1 ( talk • contribs) 10:02, 29 January 2009 (UTC)
A new Transistor channel page was recently created. After some discussion on its talk page, the original author changed it to a redirect to a FET subsection and moved the original content to Talk:Transistor channel/draft. Please review that page (with emphasis on the discussion in the talk page). The author feels that transistor channels are not adequately handled on the FET page and feels that the subject is rich enough to warrant a separate page.
I'm not quite sure I understand the argument, as a detailed discussion of the operation of unipolar channels seems identical to a detailed discussion of FET operation. So perhaps the FET page needs to be enhanced. Either way, the page was created and a discussion was started, and I think people who read this page would be interested. — TedPavlic ( talk) 14:05, 29 January 2009 (UTC)
I think this sentence contains errors. Anybody else?
"The drain and source may be doped of opposite type to the channel, in the case of enhancement mode FETs, or doped of similar type to the channel as in depletion mode FETs."
User:Vanished user 8ij3r8jwefi
15:39, 23 October 2009 (UTC)
Yes, there is a problem. "Mode" of a FET as described above is related to the POLARITY of the voltage applied to the gate with respect to source, or more accurately with respect to the gate to channel junction. All FETs have ohmic contacts at both drain and source by definition, any doping that may be there is there to ENHANCE the ohmic nature and process or design specific not a general feature.-- Murat ( talk) 19:29, 22 November 2009 (UTC)
Although the original sentence certainly simplified matters, it was basically correct as written. The supposed "correction" was blatantly wrong and confusing. It contradicts every reference I've checked which describes the structure of enhancement mode and depletion mode FETs, and it also contradicts the article's own description of how these FETs work, as well as the description of enhancement mode and depletion mode MOSFETs in the MOSFET article. I've reverted it; pity no one else caught it over the last five years. :( -- Colin Douglas Howell ( talk) 12:02, 10 September 2014 (UTC)
Perhaps the brand new NOMFET (nanoparticle organic memory field-effect transistor) should be added.
See:
http://www.physorg.com/news183373216.html
Codegrinder (
talk)
21:56, 1 February 2010 (UTC)
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I don't know enough to make appropriate corrections, but I presume BJT refers to Bipolar Junction Transistors? It would be nice if the abbreviation was introduced and the reason that they are mentioned alongside Field Effect transistors was made clear. — Preceding unsigned comment added by 128.197.40.40 ( talk) 14:32, 24 September 2012 (UTC)
Would be useful to have an image showing the common circuit symbols for a FET (at least it would have been for myself who had to do a separate search on google images after finding the wikipedia page) Norlesh ( talk) 11:05, 14 March 2014 (UTC)
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Hi guys, I'm new to the topic, and from this article (and all the others article on Wikipedia related to transistors), there is no clear explanation of the role of the body in FETs. An explanation in the section More about terminals would be greatly appreciated! Piero le fou ( talk) 19:03, 19 April 2016 (UTC)
A recent edit by 50.48.192.249 changed a statement about non-FET's being current controlled to voltage controlled devices. I feel like this should either be explained in more detail. From my knowledge of the matter, a BJT being voltage or current controlled depends on the "depth" one is willing to go and neither is strictly right or wrong. From an external perspective, yes, (in an NPN device) the voltage applied to the base-emmitor junction causes a current to flow in this PN junction. But on a "deeper" level, when you look at the junction physics, it is the electrons flowing from the emitor to the base that can then get "into" the collector before recombining in the base (asumming the base is small enough) causing a current from the collector to the emittor. In other words, a BJT cannot be boxed in as being purely "voltage" or "current" controlled, because unlike most FET's, which have a very high (and often assumed infinite) input impedance at low frequencies, making it clearly a voltage-controlled device, the BJT has a non-zero, and finite imput impeadance. In other words, It's not really a pure voltage or current controlled device.
I bring this up because I feel like this should be discussed in more detail to prevent a constant to and fro in the article. TheUnnamedNewbie ( talk) 13:46, 25 January 2017 (UTC)
I also simplified it somewhat to not go into as much depth in the introduction. TheUnnamedNewbie ( talk) 10:39, 28 January 2017 (UTC)
I corrected this in section #Effect of gate voltage on current. Even with the correction, the phrasing is poor and contains true but unnecessary information, given the purpose of the section. I'm not sure I'm qualified to edit it further.
"In a p-channel "depletion-mode" device, a positive voltage from gate to body creates a depletion layer by forcing the positively charged holes to the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions." — Preceding unsigned comment added by 173.127.144.113 ( talk) 07:33, 18 June 2018 (UTC)
An extremely rusty electronics engineer asks: if the source and drain are both doped in the same "direction" relative to the body, what actually makes them usefully different? Is it the dopant element or concentration, the geometry (e.g. penetration depth), or something completely different? MarkMLl ( talk) 20:52, 4 August 2020 (UTC)
The History section states the FET was "first patented *** in 1925", but the patent was not filed until 8 October 1926 and not issued until 28 January 1930 as shown in the approval document cited. How should the Wikipedia text be changed: to reflect the year the patent was granted or the year of filing (more interesting)... assuming the "1925" is a mistake. Myron ( talk) 23:31, 12 February 2021 (UTC)
https://www.quora.com/Can-the-drain-and-source-of-a-MOSFET-be-interchangable/answer/Jeff-Gruszynski
This answer (which looks detailed and coherent) says that MOSFETs as used in CMOS are not symmetrical.
The "Uses" section of the article currently says "The naming convention of drain terminal and source terminal is somewhat arbitrary, as the devices are typically (but not always) built symmetrical from source to drain."
If the Quora answer is correct, then the "Uses" section should be clarified.
Cphoenix ( talk) 21:16, 30 May 2022 (UTC)
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Most of what I've done here doesn't need any explanation, but there's one correction I think warrants a note. I replaced every instance of "glass" with "oxide". This is because the silicon dioxide layer under a gate is not glass. Glass would not work. A glass is an amorphous solid - irregular arrangement of atoms. The common usage of "glass" happens to be an instance of this. SiO2 in MOSFETs is crystalline, not glass. -- Tim Starling
what does "whereas those to the left abstract from the body contact." mean? It doesn't make any sense to me, or at least is doesn't convey the indended meaning, in my mind. dave
I edited the terminals section. I didn't see any discussion about it on this page. All FET's have 4 terminals (except possibly JFETs, but I'm pretty sure they do. I'll check on this and add an exception if they don't). Most of the time they are connected internally because the body effect is only useful in a couple of cases and is detrimental in most others. There are times that it doesn't matter.
The internal connection is made for three reasons. The first is to simplify circuit design. Why have a 4th terminal come out of the package if it's just going to be connected to one of the others. The second is to reduce the cost of the package. A fourth terminal adds to cost and complexity of the package, especially since there are times that you want the body to be at a very different voltage then the source. The third reason is that there is some resistance to the leads and in some cases, such as high tempreature and high current use, that resistance can cause the small current running along the body lead and the large current running along the source lead to create a measurable differential between the body and source voltages. This causes a measurable amount of difference in the threashold voltage due to the body effect, which will cause irregular switching voltages in digital circuits and plays havoc with the gain in analog circuits. By making the connection internally the designer can help to negate those effects and keep the source and body as close in voltage as possible. High frequency switching can also bring the body effect into play because there is a measurable current flowing from the gate to the body due to the capacitance.
I can think of two, possibly three, times that one would want a seperate body connection. The first is in digital designs, where you can better control the switching characteristics by connecting the body of the N-channel to the GND and the body of the P-channel to Vdd because the source may be connected to another FET's drain. The second is in analog FET switches, where one takes an N-channel and connects its drain and source in parallel with a P-channel (Although in this case they are simple FET's, which don't have a drain or source. The parasitic diode of the FET is actually designed in). The body of the P-channel goes to Vdd and the N-channel to GND. The gate of the N-channel gets driven with a signal to Vdd and the P-channel gets driven with the N-channel signal inverted. As the N-channel gate goes high, the P-channel gate goes low. This design allow the passing of analog signals higher than Vdd and lower than GND. The only limit on amplitude is Vds max. The third I am not sure about because I can't remember if biasing the base seperately gave the FET better temp characteristics or worse. It was either to stabalize it or make it into a device capable of reading tempreatue. I'll look it up and maybe find a place for it on the MOSFET page. -- Jeffrobins
I believe the following statement is incorrect:
The drain and source may be doped of opposite type to the body, in the case of enhancement mode FETs, or doped of similar type to the body as in depletion mode FETs. Field-effect transistors are also distinguished by the method of insulation between body and gate. Types of FETs are:
To my understanding the drain and source are ALWAYS doped opposite that of the body/substrate, and it is the channel that connects drain to source that is either the same (enhancement type) or the opposite (depletion type) of the body/substrate. Trashmanal 17:54, 16 May 2007 (UTC)
Good catch. The channel at the surface near the gate is what is doped to be similar to the drain and source for depletion mode. It is often adjusted in both enhancement and depletion mode. Snafflekid 23:58, 16 May 2007 (UTC)
The schematic for your MOSFET shows a solid line connecting the Source and Drain. Does this not indicate a depletion mode MOSFET?. An enhancement mode MOSFET is symbolically shown with a dashed line between the Source and Drain.
The arrows for the 'metallurgical' contacts point at the bottom of the N diffusions. The metal contact is on the top surface. Shouldn't your arrows point to the upper surface of the N regions?.
IEEE: http://ewh.ieee.org/soc/es/Nov1998/14/education/
I'm planning on doing a lot of work on the MOSFET section. I hope to discuss how MOSFETs are evolving to smaller and smaller submicron dimensions, and the problems designers are encountering...obviously non-technically. I've created two subcategories I want to expand upon--why MOSFETs are so popular and the problems with scaling. Rmalloy 13:47, 14 Jul 2004 (UTC)
I think some work needs to be done in the introduction to MOSFET...most important part. for later. Rmalloy 18:38, 14 Jul 2004 (UTC)
IMHO the external link [1] is somewhat obscure - and I'm a member of that Yahoogroup! It's neither focused on FETs nor well known. I plan to remove the link when I have some better to provide. Pjacobi 19:26, 14 Jul 2004 (UTC)
I've added all I feel comfortable adding about MOSFETs in analog circuits. I wish someone could discuss analog stuff, since everything is so digital digital digital. Rmalloy 23:38, 14 Jul 2004 (UTC)
A quesiton: "The MOSFET's strengths as the workhorse transistor in most digital circuits does not translate into supremacy in analog circuits, in which the bipolar junction transistor (BJT) has traditionally been seen as the transistor of choice, due largely to its high gain." This does not seem correct, since FETs have near-infinite gain - essentially no current flows into the gate. Glengarry 21:09, 15 Jul 2004 (UTC)
each basic circuit needs an article. common source, common drain, common gate, source follower amplifiers, etc. i can, of course, draw schematics. but i don't know these well enough to do the articles. i can start them with what i know... same for BJTs. - Omegatron 16:00, Jan 19, 2005 (UTC)
I ve not heard this one before. So we can all now use BJTs instead of FETs to create a voltage controlled resistor. I dont think so! Statement needs modifying/removing cos its wrong. Light current 04:11, 17 August 2005 (UTC)
Are you guys saying that a bipolar transistor is a voltage-controlled device? That’s wrong they are current controlled. Small base current change gives large collector current change. The FET is a voltage-controlled device. Which I like using in my projects because they are the closest things to tubes, which I cut my wisdom teeth on in the late 60's early 70's. Inkdoe 13:22, 20 October 2005
What about MFET ? Magnetic Field effect transistors, and spintronic ?
moved from page;
" Field Effect Transistor (FET) patented in 1934 by Dr. Oskar Heil. Personally first read about the FET patent year in Analog Science Fiction Science Fact magazine in the late 70s early 80s in an article about hearing aides by Larry Niven or Jerry Pournelle."
The results of what exactly Nature suggested should be corrected is out... italicize each bullet point once you make the correction. -- user:zanimum
Near the top, the article says "depletion, in which a voltage applied decreases the current flow from source to drain." This isn't true, is it? I think whoever wrote that sentence was confusing the difference between n-channel and p-channel, with the difference between enhancement mode and depletion mode. It would be more accurate to say "enhancement mode, which is normally off, when zero voltage is applied, and depletion mode, which is normally on, when zero voltage is applied." Objections to this change? -- Monguin61 17:55, 4 March 2006 (UTC)
I was wondering what the difference between an NPN transistor used in TTL logic for example, and a(n) FET transistor?
Do they not both work by applying a small current to the base to all a current to pass through?
So what are the differences between the construction/operation of an NPN transistor and a(n) FET transistor?
This page didn't really give me much help on the construction of a(n) FET transistor, as from what I see it looks EXACTLY the same as an NPN transistor. And from what I can see it works the same way too, except somehow uses energy mostly when switching states instead of during. How is it that it uses less energy than an NPN transistor?
What are the main differences between a(n) FET transistor and an NPN transistor?
How is it that an NPN transistor uses up more energy than a(n) FET transistor?
How is it that a(n) FET transistor has to be used differently for logic gates than an NPN transistor?
Thanks so much for your help! -- TAz69x 23:50, 16 April 2006 (UTC)
I have recently been investigating the process by which a PIN diode can modulate a signal as a result of incident radiation. My main point of confusion has been my inability to find any mechanical diagrams of a PIN diode which operates through the presence of 3 terminals. Most of what I have read suggests that this is a strictly 2-terminal device (the PIN in question, a Hamamatsu S5971). I came across a diagram for a FET, and was struck by not only the presence of the proper number of terminals, but the drain signal's dependence on variations in the space charge region. I am mainly curious as to the possibility that my PIN may be closer in design to an FET, through the use of the intrinsic region as the source of the drain terminal. Whether this is may be a step in the proper direction or its equally likely counterpart, I would appreciate any insight that may be offered on the subject. Jmeyers 18:39, 10 May 2006 (UTC)
I don't know of any similarity between a PiN diode and a FET. A PIN diode is a two terminal device, operated in reverse bias. Light on the diode causes carrier generation which effectively looks like a leakage current proportional to the light on the PIN diode. Even a PN junction diode does this, the largish I (intrinsic) portion just increases the area where generation occurs making it more sensitive to light. Maybe the charge coupled device is what you have in mind as a three terminal device, or a phototransistor. Snafflekid 23:34, 10 May 2006 (UTC)
It costed 2 days of research, but i finally find out that the confusion in my head came from your description of the pinch-off mode. In your description you talk about the "saturation" area, where increasing source voltage you don't have corresponding increase of drain current and you call it pinch-off ... but still there is current and its value depend on the value of the gate voltage. While the pinch-off voltage is the value of the GATE voltage for which there is no drain current at all, for any value of source-to-drain voltage (even in the ohmic region!).
see reference: http://www.st-andrews.ac.uk/~jcgl/Scots_Guide/info/comp/active/jfet/jfetchar/jfetchar.htm
152.78.72.52 20:03, 3 February 2007 (UTC)
@ 2007-02-03T21:22Z
Ok... looking around for even longer i solved my doubts, i just want to leave the observation for others: the pinch off point is indeed what you describe. In particular, for Vgate=0 is the value of Vsource=Vpo when the saturation start (the channel is "almost close"). But on the other side if Vgate=Vpo, the channel is already almost close by the bias of the gate, so the drain current "saturate" soon, for very small value, and stay almost zero for any value of Vsource. That's why it can be seen in a transconductance graph as the value of Vgate for Idrain=0. Am I right?
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Is it possible to make an animation of a saturated FET opening, where the self-consistent potential is shown as the height and some electrons as spheres running over it. Drain and gate held at fixed potential and as the source potential rises, electrons spill over?
Arnero
05:15, 1 August 2007 (UTC)
like in static image Arnero 05:33, 1 August 2007 (UTC)
You won't get a good intuition for how devices work just from reading a Wikipedia article.
fixed potential and as the source potential rises, electrons spill over?
Something like this: http://jas.eng.buffalo.edu/education/semicon/diffusion/diffusion.html ? Anyhow, the "simulation" is to time consuming for me to code, and I did not find any tool in the web. And the animation would be pretty large. Arnero 11:19, 7 August 2007 (UTC)
I'd like seconding by someone more expert than myself before making any changes; The article says (Para 5 of section 'FET Operation'); "The shape of the inversion region becomes "pinched-off" near the drain end of the channel". Unless I am mistaken, when a positive potential difference is applied between D and S the pinch region is at the source end of the channel, as the potential difference pulls the charge carriers in the inversion region (the electrons) closer to the drain (positive potential). This is corroborated by my own knowledge as well as (not explicitly) here. Comments please, Spychotic ( talk)
This is not an error actually. Channel starts pinching off near Drain side first due to the voltage drop in the channel itself.-- Murat ( talk) 19:31, 22 November 2009 (UTC)
I keep seeing references to "FETs" as an ancient predecessor to MOSFETS et al described herein. What kind of FET is one referring to then? - 143.215.155.50 ( talk) 03:55, 10 October 2008 (UTC)
Why is there no FET history section? When and how was the FET created? - 143.215.155.50 ( talk) 03:55, 10 October 2008 (UTC)
There is a lack of information regarding the physics of channel inversion ... that is when the p type semiconductor has an n type channel formed under the gate. The statemant below is wrong.. the phenomenom is not called the threshold voltage, threshold is just the voltage at which this occurs and current begins conducting through the channel... the phenomenom is called inversion.
"..........; this forms a region free of mobile carriers called a depletion region, and the phenomenon is referred to as the threshold voltage of the FET. " —Preceding unsigned comment added by Jonnic1 ( talk • contribs) 10:02, 29 January 2009 (UTC)
A new Transistor channel page was recently created. After some discussion on its talk page, the original author changed it to a redirect to a FET subsection and moved the original content to Talk:Transistor channel/draft. Please review that page (with emphasis on the discussion in the talk page). The author feels that transistor channels are not adequately handled on the FET page and feels that the subject is rich enough to warrant a separate page.
I'm not quite sure I understand the argument, as a detailed discussion of the operation of unipolar channels seems identical to a detailed discussion of FET operation. So perhaps the FET page needs to be enhanced. Either way, the page was created and a discussion was started, and I think people who read this page would be interested. — TedPavlic ( talk) 14:05, 29 January 2009 (UTC)
I think this sentence contains errors. Anybody else?
"The drain and source may be doped of opposite type to the channel, in the case of enhancement mode FETs, or doped of similar type to the channel as in depletion mode FETs."
User:Vanished user 8ij3r8jwefi
15:39, 23 October 2009 (UTC)
Yes, there is a problem. "Mode" of a FET as described above is related to the POLARITY of the voltage applied to the gate with respect to source, or more accurately with respect to the gate to channel junction. All FETs have ohmic contacts at both drain and source by definition, any doping that may be there is there to ENHANCE the ohmic nature and process or design specific not a general feature.-- Murat ( talk) 19:29, 22 November 2009 (UTC)
Although the original sentence certainly simplified matters, it was basically correct as written. The supposed "correction" was blatantly wrong and confusing. It contradicts every reference I've checked which describes the structure of enhancement mode and depletion mode FETs, and it also contradicts the article's own description of how these FETs work, as well as the description of enhancement mode and depletion mode MOSFETs in the MOSFET article. I've reverted it; pity no one else caught it over the last five years. :( -- Colin Douglas Howell ( talk) 12:02, 10 September 2014 (UTC)
Perhaps the brand new NOMFET (nanoparticle organic memory field-effect transistor) should be added.
See:
http://www.physorg.com/news183373216.html
Codegrinder (
talk)
21:56, 1 February 2010 (UTC)
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I don't know enough to make appropriate corrections, but I presume BJT refers to Bipolar Junction Transistors? It would be nice if the abbreviation was introduced and the reason that they are mentioned alongside Field Effect transistors was made clear. — Preceding unsigned comment added by 128.197.40.40 ( talk) 14:32, 24 September 2012 (UTC)
Would be useful to have an image showing the common circuit symbols for a FET (at least it would have been for myself who had to do a separate search on google images after finding the wikipedia page) Norlesh ( talk) 11:05, 14 March 2014 (UTC)
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Hi guys, I'm new to the topic, and from this article (and all the others article on Wikipedia related to transistors), there is no clear explanation of the role of the body in FETs. An explanation in the section More about terminals would be greatly appreciated! Piero le fou ( talk) 19:03, 19 April 2016 (UTC)
A recent edit by 50.48.192.249 changed a statement about non-FET's being current controlled to voltage controlled devices. I feel like this should either be explained in more detail. From my knowledge of the matter, a BJT being voltage or current controlled depends on the "depth" one is willing to go and neither is strictly right or wrong. From an external perspective, yes, (in an NPN device) the voltage applied to the base-emmitor junction causes a current to flow in this PN junction. But on a "deeper" level, when you look at the junction physics, it is the electrons flowing from the emitor to the base that can then get "into" the collector before recombining in the base (asumming the base is small enough) causing a current from the collector to the emittor. In other words, a BJT cannot be boxed in as being purely "voltage" or "current" controlled, because unlike most FET's, which have a very high (and often assumed infinite) input impedance at low frequencies, making it clearly a voltage-controlled device, the BJT has a non-zero, and finite imput impeadance. In other words, It's not really a pure voltage or current controlled device.
I bring this up because I feel like this should be discussed in more detail to prevent a constant to and fro in the article. TheUnnamedNewbie ( talk) 13:46, 25 January 2017 (UTC)
I also simplified it somewhat to not go into as much depth in the introduction. TheUnnamedNewbie ( talk) 10:39, 28 January 2017 (UTC)
I corrected this in section #Effect of gate voltage on current. Even with the correction, the phrasing is poor and contains true but unnecessary information, given the purpose of the section. I'm not sure I'm qualified to edit it further.
"In a p-channel "depletion-mode" device, a positive voltage from gate to body creates a depletion layer by forcing the positively charged holes to the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions." — Preceding unsigned comment added by 173.127.144.113 ( talk) 07:33, 18 June 2018 (UTC)
An extremely rusty electronics engineer asks: if the source and drain are both doped in the same "direction" relative to the body, what actually makes them usefully different? Is it the dopant element or concentration, the geometry (e.g. penetration depth), or something completely different? MarkMLl ( talk) 20:52, 4 August 2020 (UTC)
The History section states the FET was "first patented *** in 1925", but the patent was not filed until 8 October 1926 and not issued until 28 January 1930 as shown in the approval document cited. How should the Wikipedia text be changed: to reflect the year the patent was granted or the year of filing (more interesting)... assuming the "1925" is a mistake. Myron ( talk) 23:31, 12 February 2021 (UTC)
https://www.quora.com/Can-the-drain-and-source-of-a-MOSFET-be-interchangable/answer/Jeff-Gruszynski
This answer (which looks detailed and coherent) says that MOSFETs as used in CMOS are not symmetrical.
The "Uses" section of the article currently says "The naming convention of drain terminal and source terminal is somewhat arbitrary, as the devices are typically (but not always) built symmetrical from source to drain."
If the Quora answer is correct, then the "Uses" section should be clarified.
Cphoenix ( talk) 21:16, 30 May 2022 (UTC)
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