This article is rated B-class on Wikipedia's
content assessment scale. It is of interest to the following WikiProjects: | ||||||||||||||
|
Archives ( Index) |
This page is archived by
ClueBot III.
|
See comments added to /info/en/?search=Talk:DEC_PRISM#The_article_is_wrong_about_how_MIPS_got_chosen This gives some key history on how MIPS got into DEC product line, starting with a chance meeting at 1988 computer show in Washington that caused Ultrix to be ported to Little-Endian-configured MIPS M/1000s loaned to DEC in New Hampshire. JohnMashey ( talk) 23:56, 23 June 2021 (UTC)
The Design Principles section talks about "Suppressed instructions", but that doesn't seem to be a technical term. Should that be predication? (Even then, a source is missing to back up the claim that the lack of predication is related to multiple instruction issue, clock rate or multiprocessing.) Nbgl ( talk) 03:24, 16 January 2023 (UTC)
The Alpha AXP architecture has no suppressed instructions, whereby the execution of one instruction conditionally suppresses a following one.
This article is rated B-class on Wikipedia's
content assessment scale. It is of interest to the following WikiProjects: | ||||||||||||||
|
Archives ( Index) |
This page is archived by
ClueBot III.
|
See comments added to /info/en/?search=Talk:DEC_PRISM#The_article_is_wrong_about_how_MIPS_got_chosen This gives some key history on how MIPS got into DEC product line, starting with a chance meeting at 1988 computer show in Washington that caused Ultrix to be ported to Little-Endian-configured MIPS M/1000s loaned to DEC in New Hampshire. JohnMashey ( talk) 23:56, 23 June 2021 (UTC)
The Design Principles section talks about "Suppressed instructions", but that doesn't seem to be a technical term. Should that be predication? (Even then, a source is missing to back up the claim that the lack of predication is related to multiple instruction issue, clock rate or multiprocessing.) Nbgl ( talk) 03:24, 16 January 2023 (UTC)
The Alpha AXP architecture has no suppressed instructions, whereby the execution of one instruction conditionally suppresses a following one.