Text on this page is word for word identical this: http://www.numascale.com/directory-based.html - which of course may be copied from Wikipedia (but no acknowledgement is given). Either way I suspect this page could be rewritten. 81.178.193.87 ( talk) 19:12, 17 November 2012 (UTC)
This article should not be merged with cache. Cache coherency is a distinct topic. Dennis 20:01, 18 Dec 2004 (UTC)
Whoever wrote this needs to go back and make a couple of changes:
1. Cache consistency != cache coherency
Coherency has to do with what values can be returned from a read, consistency has to do with the propagation of writes and when written values can/will be returned by a read. Read Hennessey and Patteron's book Ch6 to get an overview.
2. It might be nice to give some different examples of different CC protocols. The three major families of protocols are broadcast snoop, directory based, and hybrid (the only hybrid I know of is the IBM X3, see http://www.realworldtech.com/includes/templates/articles.cfm?ArticleID=RWT042405213553&mode=print for a description of the hybrid broadcast, directory protocol.
David Kanter
I think the article should be generalized to apply to any kind of cache, and make a clear distinction when it's speaking about the CPU cache and when not. I have also added the
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{{ mergefrom}} tag for caching failure, as it is an artifact of cache incoherency. -- intgr 11:37, 6 December 2006 (UTC)
Please do not merge cache failure into this article. Cache incoherency can lead to cache failure however as the that is but one of the many causes. Cache failure article also gives examples of failures in web browser caching that have nothing to do with coherency as defined today. — Preceding unsigned comment added by 71.236.225.96 ( talk)
This article doesn't talk about strategies like:
-- Beland 23:02, 15 May 2007 (UTC)
There is also a lot of discussion of the specific application of CPU/memory data caching, which assumes this is the only application. It would be good to make the language more inclusive and add examples from different applications. -- Beland 23:08, 15 May 2007 (UTC)
-- Kubanczyk 18:41, 7 September 2007 (UTC)
Also, the author has to define snarfing clearly —Preceding unsigned comment added by Jayendran.ramani ( talk • contribs) 12:08, 24 March 2009 (UTC)
Dumb question. Since the text of the article consistently uses the spelling "cache coherence", why is the article "Cache coherency"? -- Jorend 00:43, 26 October 2007 (UTC)
And is "coherency" even a word? Blowfish ( talk) 21:55, 10 November 2008 (UTC)
How do directory-based cache coherence protocols work? -- Abdull ( talk) 15:39, 9 August 2008 (UTC)
The Coherence protocol article is almost empty, all the existing information fits here in existing subsections, and cache coherence seems to me impossible to discuss without discussing coherence protocols. What do you think? -- Blaisorblade ( talk) 09:57, 28 December 2008 (UTC)
I agree with this suggestion. I would append that coherence protocol be left with a redirect to this article. —Preceding unsigned comment added by 164.106.166.49 ( talk)
AMD uses MOESI in opteron, Intel - MESI in pentium & Core. What protocols are used by other vendors? Such information can be added into article. —Preceding unsigned comment added by A5b ( talk • contribs)
<ref>http://your.link.here/...</ref>
. --
intgr
[talk]
17:13, 9 October 2009 (UTC)Minor note: shouldn't the "Illinois" and "MESI" items in the protocol list be replaced by one item "MESI (Illinois) protocol"? They refer to the same thing, and it is not clear why have two entries in the list. —Preceding unsigned comment added by Alexeicolin ( talk • contribs) 13:50, 25 March 2010 (UTC)
Insertion of "and" is incorrect in "Different processors may see an operand and assume different sequences of values.", although more than one editor (lately @ Intgr:) has introduced it. I am surprised this should be contentious as the sentence jarred with me on first reading it. It seemed so simple at the time.
Both forms are grammatically correct (nearly) but they differ in meaning: the subject of the verb "assume" is changed. The version without "and" is correct because:
Better than either is "Different processors may each see an operand assume a different sequence of values." The singular is to be preferred because each processor sees one particular sequence.
-- Prof Tournesol ( talk) 06:25, 19 December 2015 (UTC)
The article says: "The cache coherence problem exists only in systems with private local caches." I claim this isn't true. Assume a CPU with 4 cores and 2 levels of cache. One L1 cache (L1.0) is shared between CPU0 and CPU1, another one (L1.1) is shared between CPU2 and CPU3. L2 is shared between all 4 cores. Therefore, there aren't any private local caches and according to the statement I'm challenging, there can't be a cache coherence problem. But suppose a thread running on CPU0 reads a variable and a different one running on CPU2 accesses the same one pretty much at the same time. Both L1.0 and L1.1 contain a cache line holding that variable. If now both processes modify the variable, we have a cache coherence problem. — Preceding unsigned comment added by McGucket ( talk • contribs) 22:25, 13 December 2016 (UTC)
i find that this article should speak also about software coherency and mention that directory based and snoop protocols are hardware based cache coherency protocols — Preceding unsigned comment added by 2001:660:6302:21:6495:BC40:E65D:45DD ( talk) 11:18, 15 September 2017 (UTC)
Hello fellow Wikipedians,
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I am confused by "In a read made by a processor P to a location X". As a native English speaker it seems that this should read "In a read made by a processor P from a location X".
Is there some technical reason for using "to" for both reads and writes?
Thanks,
-kb
(I'm trying to understand "false sharing" and getting really clear on cache coherency seems a necessary prerequisite. Using a clearer preposition here would help. I'm happy to make the change, but want to make sure I'm not breaking something else I don't appreciate.) Kentborg ( talk) 17:13, 27 July 2023 (UTC)
COI - It is my idea, but it has not been modeled, so no product exists. This is informational only. It has been peer reviewed.
I would like to propose an entry under coherence mechanisms, a coherence-free processor.
It might be possible to create an
exclusive cache. This would make possible a coherence-free processor.
FrankYang43338 (
talk)
16:21, 23 March 2024 (UTC)
If there were two types of data, then it might be faster to process them in different ways.
Just as a car performs better when you match the tires to the weather,
a computer can execute faster when the algorithm is optimized for each data type.
See also:
WIPO patent
and
my sandbox.
Thank you for assisting.
FrankYang43338 (
talk)
13:02, 13 April 2024 (UTC)
Text on this page is word for word identical this: http://www.numascale.com/directory-based.html - which of course may be copied from Wikipedia (but no acknowledgement is given). Either way I suspect this page could be rewritten. 81.178.193.87 ( talk) 19:12, 17 November 2012 (UTC)
This article should not be merged with cache. Cache coherency is a distinct topic. Dennis 20:01, 18 Dec 2004 (UTC)
Whoever wrote this needs to go back and make a couple of changes:
1. Cache consistency != cache coherency
Coherency has to do with what values can be returned from a read, consistency has to do with the propagation of writes and when written values can/will be returned by a read. Read Hennessey and Patteron's book Ch6 to get an overview.
2. It might be nice to give some different examples of different CC protocols. The three major families of protocols are broadcast snoop, directory based, and hybrid (the only hybrid I know of is the IBM X3, see http://www.realworldtech.com/includes/templates/articles.cfm?ArticleID=RWT042405213553&mode=print for a description of the hybrid broadcast, directory protocol.
David Kanter
I think the article should be generalized to apply to any kind of cache, and make a clear distinction when it's speaking about the CPU cache and when not. I have also added the
This
level-5 vital article is rated Start-class on Wikipedia's
content assessment scale. It is of interest to the following WikiProjects: | |||||||||||
|
{{ mergefrom}} tag for caching failure, as it is an artifact of cache incoherency. -- intgr 11:37, 6 December 2006 (UTC)
Please do not merge cache failure into this article. Cache incoherency can lead to cache failure however as the that is but one of the many causes. Cache failure article also gives examples of failures in web browser caching that have nothing to do with coherency as defined today. — Preceding unsigned comment added by 71.236.225.96 ( talk)
This article doesn't talk about strategies like:
-- Beland 23:02, 15 May 2007 (UTC)
There is also a lot of discussion of the specific application of CPU/memory data caching, which assumes this is the only application. It would be good to make the language more inclusive and add examples from different applications. -- Beland 23:08, 15 May 2007 (UTC)
-- Kubanczyk 18:41, 7 September 2007 (UTC)
Also, the author has to define snarfing clearly —Preceding unsigned comment added by Jayendran.ramani ( talk • contribs) 12:08, 24 March 2009 (UTC)
Dumb question. Since the text of the article consistently uses the spelling "cache coherence", why is the article "Cache coherency"? -- Jorend 00:43, 26 October 2007 (UTC)
And is "coherency" even a word? Blowfish ( talk) 21:55, 10 November 2008 (UTC)
How do directory-based cache coherence protocols work? -- Abdull ( talk) 15:39, 9 August 2008 (UTC)
The Coherence protocol article is almost empty, all the existing information fits here in existing subsections, and cache coherence seems to me impossible to discuss without discussing coherence protocols. What do you think? -- Blaisorblade ( talk) 09:57, 28 December 2008 (UTC)
I agree with this suggestion. I would append that coherence protocol be left with a redirect to this article. —Preceding unsigned comment added by 164.106.166.49 ( talk)
AMD uses MOESI in opteron, Intel - MESI in pentium & Core. What protocols are used by other vendors? Such information can be added into article. —Preceding unsigned comment added by A5b ( talk • contribs)
<ref>http://your.link.here/...</ref>
. --
intgr
[talk]
17:13, 9 October 2009 (UTC)Minor note: shouldn't the "Illinois" and "MESI" items in the protocol list be replaced by one item "MESI (Illinois) protocol"? They refer to the same thing, and it is not clear why have two entries in the list. —Preceding unsigned comment added by Alexeicolin ( talk • contribs) 13:50, 25 March 2010 (UTC)
Insertion of "and" is incorrect in "Different processors may see an operand and assume different sequences of values.", although more than one editor (lately @ Intgr:) has introduced it. I am surprised this should be contentious as the sentence jarred with me on first reading it. It seemed so simple at the time.
Both forms are grammatically correct (nearly) but they differ in meaning: the subject of the verb "assume" is changed. The version without "and" is correct because:
Better than either is "Different processors may each see an operand assume a different sequence of values." The singular is to be preferred because each processor sees one particular sequence.
-- Prof Tournesol ( talk) 06:25, 19 December 2015 (UTC)
The article says: "The cache coherence problem exists only in systems with private local caches." I claim this isn't true. Assume a CPU with 4 cores and 2 levels of cache. One L1 cache (L1.0) is shared between CPU0 and CPU1, another one (L1.1) is shared between CPU2 and CPU3. L2 is shared between all 4 cores. Therefore, there aren't any private local caches and according to the statement I'm challenging, there can't be a cache coherence problem. But suppose a thread running on CPU0 reads a variable and a different one running on CPU2 accesses the same one pretty much at the same time. Both L1.0 and L1.1 contain a cache line holding that variable. If now both processes modify the variable, we have a cache coherence problem. — Preceding unsigned comment added by McGucket ( talk • contribs) 22:25, 13 December 2016 (UTC)
i find that this article should speak also about software coherency and mention that directory based and snoop protocols are hardware based cache coherency protocols — Preceding unsigned comment added by 2001:660:6302:21:6495:BC40:E65D:45DD ( talk) 11:18, 15 September 2017 (UTC)
Hello fellow Wikipedians,
I have just modified one external link on Cache coherence. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.
This message was posted before February 2018.
After February 2018, "External links modified" talk page sections are no longer generated or monitored by InternetArchiveBot. No special action is required regarding these talk page notices, other than
regular verification using the archive tool instructions below. Editors
have permission to delete these "External links modified" talk page sections if they want to de-clutter talk pages, but see the
RfC before doing mass systematic removals. This message is updated dynamically through the template {{
source check}}
(last update: 5 June 2024).
Cheers.— InternetArchiveBot ( Report bug) 22:28, 6 December 2017 (UTC)
I am confused by "In a read made by a processor P to a location X". As a native English speaker it seems that this should read "In a read made by a processor P from a location X".
Is there some technical reason for using "to" for both reads and writes?
Thanks,
-kb
(I'm trying to understand "false sharing" and getting really clear on cache coherency seems a necessary prerequisite. Using a clearer preposition here would help. I'm happy to make the change, but want to make sure I'm not breaking something else I don't appreciate.) Kentborg ( talk) 17:13, 27 July 2023 (UTC)
COI - It is my idea, but it has not been modeled, so no product exists. This is informational only. It has been peer reviewed.
I would like to propose an entry under coherence mechanisms, a coherence-free processor.
It might be possible to create an
exclusive cache. This would make possible a coherence-free processor.
FrankYang43338 (
talk)
16:21, 23 March 2024 (UTC)
If there were two types of data, then it might be faster to process them in different ways.
Just as a car performs better when you match the tires to the weather,
a computer can execute faster when the algorithm is optimized for each data type.
See also:
WIPO patent
and
my sandbox.
Thank you for assisting.
FrankYang43338 (
talk)
13:02, 13 April 2024 (UTC)