From Wikipedia, the free encyclopedia
MB86900
General information
Launched1986
Designed by Fujitsu
Performance
Max. CPU clock rate16.67 MHz
Architecture and classification
Instruction set SPARC V7
Physical specifications
Cores
  • 1

The MB86900 is a microprocessor produced by Fujitsu, [1] which implements the SPARC V7 instruction set architecture developed by Sun Microsystems. It was the first implementation of SPARC, introduced in 1986, and was used in the first SPARC-based workstation, the Sun Microsystems Sun-4, from 1987. [2] [3] Its chipset operated at 16.67 MHz. The chipset consisted of two chips, the MB86900 microprocessor and the MB86910 floating-point unit. The chip set was implemented with two 20,000-gate, 1.2 μm complementary metal–oxide–semiconductor (CMOS) gate-arrays fabricated by Fujitsu Limited.

Notes

  1. ^ "Fujitsu to take ARM into the realm of Super". The CPU Shack Museum. June 21, 2016. Retrieved 30 June 2019.
  2. ^ "Fujitsu SPARC". cpu-collection.de. Retrieved 30 June 2019.
  3. ^ "Timeline". SPARC International. Retrieved 30 June 2019.

References

  • Quach, L.; Chueh, R. (1988). "CMOS gate array implementation of SPARC". Thirty-Third IEEE Computer Society International Conference, Digest of Papers.
  • Namjoo, M. (1989). "SPARC implementations: ASIC vs. custom design". Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences.
From Wikipedia, the free encyclopedia
MB86900
General information
Launched1986
Designed by Fujitsu
Performance
Max. CPU clock rate16.67 MHz
Architecture and classification
Instruction set SPARC V7
Physical specifications
Cores
  • 1

The MB86900 is a microprocessor produced by Fujitsu, [1] which implements the SPARC V7 instruction set architecture developed by Sun Microsystems. It was the first implementation of SPARC, introduced in 1986, and was used in the first SPARC-based workstation, the Sun Microsystems Sun-4, from 1987. [2] [3] Its chipset operated at 16.67 MHz. The chipset consisted of two chips, the MB86900 microprocessor and the MB86910 floating-point unit. The chip set was implemented with two 20,000-gate, 1.2 μm complementary metal–oxide–semiconductor (CMOS) gate-arrays fabricated by Fujitsu Limited.

Notes

  1. ^ "Fujitsu to take ARM into the realm of Super". The CPU Shack Museum. June 21, 2016. Retrieved 30 June 2019.
  2. ^ "Fujitsu SPARC". cpu-collection.de. Retrieved 30 June 2019.
  3. ^ "Timeline". SPARC International. Retrieved 30 June 2019.

References

  • Quach, L.; Chueh, R. (1988). "CMOS gate array implementation of SPARC". Thirty-Third IEEE Computer Society International Conference, Digest of Papers.
  • Namjoo, M. (1989). "SPARC implementations: ASIC vs. custom design". Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences.

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