In computer engineering, a loadâstore architecture (or a registerâregister architecture) is an instruction set architecture that divides instructions into two categories: memory access ( load and store between memory and registers) and ALU operations (which only occur between registers). [1]: 9â12
Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are loadâstore architectures. [1]: 9â12
For instance, in a loadâstore approach both operands and destination for an ADD operation must be in registers. This differs from a registerâmemory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register. [1]: 9â12
The earliest example of a loadâstore architecture was the CDC 6600. [1]: 54â56 Almost all vector processors (including many GPUs [2][ better source needed]) use the loadâstore approach. [3]
In computer engineering, a loadâstore architecture (or a registerâregister architecture) is an instruction set architecture that divides instructions into two categories: memory access ( load and store between memory and registers) and ALU operations (which only occur between registers). [1]: 9â12
Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are loadâstore architectures. [1]: 9â12
For instance, in a loadâstore approach both operands and destination for an ADD operation must be in registers. This differs from a registerâmemory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register. [1]: 9â12
The earliest example of a loadâstore architecture was the CDC 6600. [1]: 54â56 Almost all vector processors (including many GPUs [2][ better source needed]) use the loadâstore approach. [3]