Intel SHA Extensions are a set of extensions to the x86 instruction set architecture which support hardware acceleration of Secure Hash Algorithm (SHA) family. It was introduced in 2013. Instructions for SHA-512 will be introduced in Arrow Lake and Lunar Lake in 2024.
The original
SSE-based extensions added four instructions supporting
SHA-1 and three for
SHA-256.
AVX-based versions are also available with a V prefix.
- SHA-1:
SHA1RNDS4,SHA1NEXTE,SHA1MSG1,SHA1MSG2 - SHA-256:
SHA256RNDS2,SHA256MSG1,SHA256MSG2
The AVX-based extensions added three for SHA-512.
VSHA512RNDS2,VSHA512MSG1,VSHA512MSG2
x86 architecture processors
Intel
The following Intel processors support the original SHA instruction set:
- Intel Goldmont (and later Atom microarchitectures) processors. [1]
- Intel Ice Lake (and later) processors. [2]
- Intel Rocket Lake (and later) processors.
The following Intel processors will support the newer SHA-512 instruction set:
- Intel Arrow Lake and Lunar Lake processors.
AMD
Several AMD processors support the original SHA instruction set:
References
- ^ "Goldmont - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2020-06-26.
- ^ "Ice Lake (client) - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2020-06-26.
- ^ "Zen - Microarchitectures - AMD - WikiChip". en.wikichip.org. Retrieved 2020-06-26.
External links
- New Instructions Supporting the Secure Hash Algorithm on Intel® Architecture Processors
- Intel Instruction Set Architecture Extensions
- "Intel Architecture Instruction Set Extensions Programming Reference" (PDF). Archived from the original (PDF) on 2013-09-29., Chapter 8
 | This microcomputer- or microprocessor-related article is a stub. You can help Wikipedia by expanding it. |
Intel SHA Extensions are a set of extensions to the x86 instruction set architecture which support hardware acceleration of Secure Hash Algorithm (SHA) family. It was introduced in 2013. Instructions for SHA-512 will be introduced in Arrow Lake and Lunar Lake in 2024.
The original
SSE-based extensions added four instructions supporting
SHA-1 and three for
SHA-256.
AVX-based versions are also available with a V prefix.
- SHA-1:
SHA1RNDS4,SHA1NEXTE,SHA1MSG1,SHA1MSG2 - SHA-256:
SHA256RNDS2,SHA256MSG1,SHA256MSG2
The AVX-based extensions added three for SHA-512.
VSHA512RNDS2,VSHA512MSG1,VSHA512MSG2
x86 architecture processors
Intel
The following Intel processors support the original SHA instruction set:
- Intel Goldmont (and later Atom microarchitectures) processors. [1]
- Intel Ice Lake (and later) processors. [2]
- Intel Rocket Lake (and later) processors.
The following Intel processors will support the newer SHA-512 instruction set:
- Intel Arrow Lake and Lunar Lake processors.
AMD
Several AMD processors support the original SHA instruction set:
References
- ^ "Goldmont - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2020-06-26.
- ^ "Ice Lake (client) - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2020-06-26.
- ^ "Zen - Microarchitectures - AMD - WikiChip". en.wikichip.org. Retrieved 2020-06-26.
External links
- New Instructions Supporting the Secure Hash Algorithm on Intel® Architecture Processors
- Intel Instruction Set Architecture Extensions
- "Intel Architecture Instruction Set Extensions Programming Reference" (PDF). Archived from the original (PDF) on 2013-09-29., Chapter 8
|
| This microcomputer- or microprocessor-related article is a stub. You can help Wikipedia by expanding it. |