General information | |
---|---|
Launched | 2018 [1] |
Designed by | ARM Holdings |
Performance | |
Max. CPU clock rate | to 3.0 GHz in phones and 3.3 GHz in tablets/laptops |
FSB speeds | 100 to 104 |
Address width | 40-bit |
Cache | |
L1 cache | 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
L2 cache | 128–512 KiB per core |
L3 cache | 512 KiB–4 MiB (optional) |
Architecture and classification | |
Microarchitecture | ARM Cortex-A76 |
Instruction set | ARMv8-A: A64, A32, and T32 (at the EL0 only) |
Extensions | |
Physical specifications | |
Cores |
|
Co-processor | ARM Cortex-A55 (optional) |
Products, models, variants | |
Product code name |
|
Variant | |
History | |
Predecessors |
ARM Cortex-A75 ARM Cortex-A73 ARM Cortex-A72 |
Successor | ARM Cortex-A77 |
The ARM Cortex-A76 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM states a 25% and 35% increase in integer and floating point performance, respectively, over a Cortex-A75 of the previous generation. [2]
The Cortex-A76 serves as the successor of the ARM Cortex-A73 and ARM Cortex-A75, though based on a clean sheet design.
The Cortex-A76 frontend is a 4-wide decode out-of-order superscalar design. It can fetch 4 instructions per cycle. And[ clarification needed] rename and dispatch 4 Mops, and 8 μops per cycle. The out-of-order window size is 128 entries. The backend is 8 execution ports[ clarification needed] with a pipeline depth of 13 stages and the execution latencies of 11 stages. [2] [3]
The core supports unprivileged 32-bit applications, but privileged applications must utilize the 64-bit ARMv8-A ISA. [4] It also supports Load acquire (LDAPR) instructions ( ARMv8.3-A), Dot Product instructions ( ARMv8.4-A), PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB, PSSBB) instructions ( ARMv8.5-A). [5]
Memory bandwidth increased 90% relative to the A75. [6] [7] According to ARM, the A76 is expected to offer twice the performance of an A73 and is targeted beyond mobile workloads. The performance is targeted at " laptop class", including Windows 10 devices, [8] competitive with Intel's Kaby Lake. [9]
The Cortex-A76 support ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with Cortex-A55 power-efficient cores. [2]
The Cortex-A76 is available as a SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
The Cortex-A76 was first used in the HiSilicon Kirin 980. [10]
ARM has also collaborated with Qualcomm for a semi-custom version of the Cortex-A76, used within their high-end Kryo 495 (Snapdragon 8cx)/ Kryo 485 (Snapdragon 855 and 855 Plus), and also in their mid-range Kryo 460 (Snapdragon 675) and Kryo 470 (Snapdragon 730) CPUs. One of the modifications Qualcomm made was increasing reorder buffer to increase the out-of-order window size. [11]
It is also used in the Exynos 990 and Exynos Auto V9, [12] the MediaTek Helio G90/G90T/G95/G99 and Dimensity 800 and Dimensity 820, and the HiSilicon Kirin 985 5G and Kirin 990 4G/990 5G/990E 5G. [13] [14] [15]
The Cortex-A76 can be found in Snapdragon 855 as Big-core.
The Cortex-A76 is used as Big-core in Intel Agilex D-series SoC FPGA devices. [16]
In 2020 Cortex-A76 was used in Rockchip RK3588 and RK3588s.
In September 2023, the Raspberry Pi 5 was introduced with a Broadcom BCM2712 quad-core Arm Cortex-A76 processor with a clock speed of 2.4 GHz. [17]
General information | |
---|---|
Launched | 2018 [1] |
Designed by | ARM Holdings |
Performance | |
Max. CPU clock rate | to 3.0 GHz in phones and 3.3 GHz in tablets/laptops |
FSB speeds | 100 to 104 |
Address width | 40-bit |
Cache | |
L1 cache | 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
L2 cache | 128–512 KiB per core |
L3 cache | 512 KiB–4 MiB (optional) |
Architecture and classification | |
Microarchitecture | ARM Cortex-A76 |
Instruction set | ARMv8-A: A64, A32, and T32 (at the EL0 only) |
Extensions | |
Physical specifications | |
Cores |
|
Co-processor | ARM Cortex-A55 (optional) |
Products, models, variants | |
Product code name |
|
Variant | |
History | |
Predecessors |
ARM Cortex-A75 ARM Cortex-A73 ARM Cortex-A72 |
Successor | ARM Cortex-A77 |
The ARM Cortex-A76 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM states a 25% and 35% increase in integer and floating point performance, respectively, over a Cortex-A75 of the previous generation. [2]
The Cortex-A76 serves as the successor of the ARM Cortex-A73 and ARM Cortex-A75, though based on a clean sheet design.
The Cortex-A76 frontend is a 4-wide decode out-of-order superscalar design. It can fetch 4 instructions per cycle. And[ clarification needed] rename and dispatch 4 Mops, and 8 μops per cycle. The out-of-order window size is 128 entries. The backend is 8 execution ports[ clarification needed] with a pipeline depth of 13 stages and the execution latencies of 11 stages. [2] [3]
The core supports unprivileged 32-bit applications, but privileged applications must utilize the 64-bit ARMv8-A ISA. [4] It also supports Load acquire (LDAPR) instructions ( ARMv8.3-A), Dot Product instructions ( ARMv8.4-A), PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB, PSSBB) instructions ( ARMv8.5-A). [5]
Memory bandwidth increased 90% relative to the A75. [6] [7] According to ARM, the A76 is expected to offer twice the performance of an A73 and is targeted beyond mobile workloads. The performance is targeted at " laptop class", including Windows 10 devices, [8] competitive with Intel's Kaby Lake. [9]
The Cortex-A76 support ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with Cortex-A55 power-efficient cores. [2]
The Cortex-A76 is available as a SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
The Cortex-A76 was first used in the HiSilicon Kirin 980. [10]
ARM has also collaborated with Qualcomm for a semi-custom version of the Cortex-A76, used within their high-end Kryo 495 (Snapdragon 8cx)/ Kryo 485 (Snapdragon 855 and 855 Plus), and also in their mid-range Kryo 460 (Snapdragon 675) and Kryo 470 (Snapdragon 730) CPUs. One of the modifications Qualcomm made was increasing reorder buffer to increase the out-of-order window size. [11]
It is also used in the Exynos 990 and Exynos Auto V9, [12] the MediaTek Helio G90/G90T/G95/G99 and Dimensity 800 and Dimensity 820, and the HiSilicon Kirin 985 5G and Kirin 990 4G/990 5G/990E 5G. [13] [14] [15]
The Cortex-A76 can be found in Snapdragon 855 as Big-core.
The Cortex-A76 is used as Big-core in Intel Agilex D-series SoC FPGA devices. [16]
In 2020 Cortex-A76 was used in Rockchip RK3588 and RK3588s.
In September 2023, the Raspberry Pi 5 was introduced with a Broadcom BCM2712 quad-core Arm Cortex-A76 processor with a clock speed of 2.4 GHz. [17]