General information | |
---|---|
Common manufacturer(s) | |
Architecture and classification | |
Instruction set | AMD64 ( x86-64) |
History | |
Predecessor(s) | K8 - SledgeHammer |
Successor(s) | AMD K10 |
This article may need to be rewritten to comply with Wikipedia's
quality standards. (May 2009) |
The AMD K9 represents a microarchitecture by AMD designed to replace the K8 processors, featuring dual-core processing.
K9 appears originally to have been an ambitious 8 issue per clock cycle core redesign of the K7 or the K8 processor core. [1] At one point, K9 was the Greyhound project at AMD, and was worked on by the K7 design team beginning in early 2001, with tape-out revision A0 scheduled for 2003. The L1 instruction cache was said to hold decoded instructions, essentially the same as Intel's trace cache.
The existence of a massively parallel CPU design concept for heavily multi threaded applications has also been revealed, as a planned successor to K8. This was reportedly canceled in the conceptualization phase, after about 6 months' work. [2]
At one time K9 was the internal codename for the dual-core AMD64 processors as the brand Athlon 64 X2; [3] [4] however, AMD has distanced itself from the old K series naming convention, and now seeks to talk about a portfolio of products tailored to different markets. [5]
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cite web}}
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General information | |
---|---|
Common manufacturer(s) | |
Architecture and classification | |
Instruction set | AMD64 ( x86-64) |
History | |
Predecessor(s) | K8 - SledgeHammer |
Successor(s) | AMD K10 |
This article may need to be rewritten to comply with Wikipedia's
quality standards. (May 2009) |
The AMD K9 represents a microarchitecture by AMD designed to replace the K8 processors, featuring dual-core processing.
K9 appears originally to have been an ambitious 8 issue per clock cycle core redesign of the K7 or the K8 processor core. [1] At one point, K9 was the Greyhound project at AMD, and was worked on by the K7 design team beginning in early 2001, with tape-out revision A0 scheduled for 2003. The L1 instruction cache was said to hold decoded instructions, essentially the same as Intel's trace cache.
The existence of a massively parallel CPU design concept for heavily multi threaded applications has also been revealed, as a planned successor to K8. This was reportedly canceled in the conceptualization phase, after about 6 months' work. [2]
At one time K9 was the internal codename for the dual-core AMD64 processors as the brand Athlon 64 X2; [3] [4] however, AMD has distanced itself from the old K series naming convention, and now seeks to talk about a portfolio of products tailored to different markets. [5]
{{
cite web}}
: CS1 maint: unfit URL (
link)
{{
cite web}}
: CS1 maint: unfit URL (
link)